Abstract: The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and a second sidewall wherein the first sidewall is opposite the second sidewall. The first sidewall has a stair step configuration such that the first sidewall is closer to the second sidewall at the bottom of the opening than at the top of the opening. A conductive film is then formed on the first sidewall in the opening and on the bottom of the opening on the conductive film.

Abstract: The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features. The gap between the features is filled with the dielectric material which is softer than the masking layer with respect to a planarization step. The dielectric material is then planarized with the masking layer acting as a polish stop.

Abstract: The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure.

Abstract: In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a respective test memory cell at the far end of each respective bit line relative to its bit line driver. An intra-layer short between word lines may be detected, such as during manufacturing testing, by biasing adjacent word lines to different voltages and detecting whether any leakage current flowing from one to another exceeds that normally accounted for by the memory cells and other known circuits. Intra-layer bit line shorts and inter-layer word line and bit line shorts may also be similarly detected. An “open” in a word line or bit line may be detected by trying to program the test memory cell at the far end of each such word line or bit line.

Abstract: An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

Abstract: An arithmetic unit for adding a plurality of values to define a result, said arithmetic unit comprising means for receiving said plurality of values; means for adding said plurality of values to define a result, said result being within a first range; means for determining if said result fall within a second range, said second range being smaller than the first range, said means being arranged to consider only some of the bits of said result; and means for modifying said result in so that the result output by said arithmetic unit falls within the second range.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: An electron-emitting device contains a vertical emitter resistor patterned into multiple laterally separated sections (34, 34V, 46, or 46V) situated between the electron-emissive elements (40), on one hand, and emitter electrodes (32), on the other hand. Sections of the resistor are spaced apart along each emitter electrode.

Abstract: A trench-isolated active device and a method of forming a trench-isolated active device on a semiconductor substrate wherein the conductive layer of the device is self-aligned with an isolation trench is disclosed. The method includes applying a conductive layer over a dielectric layer (e.g., gate oxide), forming an opening in the conductive layer and the dielectric layer, forming a trench in the substrate corresponding to the opening, passivating the side walls of the trench with a dielectric material, and filling the trench with a dielectric material. The structure includes a semiconductor substrate having a trench defining a cell region, conductive material in the cell region and adjacent to the trench, and a layer of dielectric material on the side walls of the trench and on the conductive material adjacent to the trench. The invention further contemplates that the trench contains dielectric material, preferably soft glass.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (102A, 110A, 124A, 140, or 150B). Dielectric openings (80, 114, 128, 144, or 154) are formed through the insulating layer. The dielectric openings can be created before or after creating the spacers.

Abstract: The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Abstract: The present invention describes a method for forming an interconnect to a region of an electronic device. The method comprises the steps of: forming a conductive material layer, wherein the conductive material layer fills an opening in a first dielectric layer and is disposed over the first dielectric layer; applying a patterning layer over the conductive material layer, wherein the patterning layer exposes a portion of the conductive material layer; etching the conductive material layer to remove the portion of the conductive material layer in order to provide an exposed conductive material structure that protrudes above the dielectric layer; forming a second dielectric layer; and planarizing the second dielectric layer to expose a portion of the exposed conductive material structure.

Abstract: A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (110A, 124A, 140, or 150B) but leave corresponding apertures (112A, 126A, 142, or 152) through the spacer material. The insulating layer is etched through the apertures to form dielectric openings (114, 128, 144, or 154) through the insulating layer. Emitter material is introduced into the dielectric openings to form electron-emissive elements (116B, 130A, 146A, or 156B) typically filamentary in shape.

Abstract: A damascene method of forming planarized interconnects between conductive material layers in trench-isolated cells in an integrated circuit is disclosed. The method includes depositing and patterning a photoresist layer over a portion of an integrated circuit with isolated devices to expose a portion of an isolation trench separating the conductive layers of isolated devices desired to be interconnected. The method further involves etching a portion of the trench refill material, removing the photoresist layer, and depositing a second conductive layer in the trench to replace the material removed by the etching step.

Abstract: A method of encapsulating a dielectric. According to the method of the present invention, a disposable post is formed over a portion of a substrate. Next, a first dielectric layer is formed over the substrate and the disposable post. A second dielectric layer is then formed over the first dielectric layer. Next, a third dielectric layer is formed over the second dielectric layer. A portion of the third dielectric layer is then removed so as to reveal the disposable post. The disposable post is then removed to form an opening.