Patents by Inventor James M. Cleeves

James M. Cleeves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dense arrays and charge storage devices
    Publication number: 20090173985
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 9, 2009
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Peti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald
  • OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE
    Publication number: 20080310231
    Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 18, 2008
    Inventors: James M. Cleeves, Roy E. Scheuerlein
  • Memory cell with high-K antifuse for reverse bias programming
    Patent number: 7453755
    Abstract: An integrated circuit and associated method of programming are provided. Such integrated circuit includes a memory cell with a diode and an antifuse in communication with the diode. The antifuse is constructed to include a high-K dielectric material with a K greater than 3.9. Further, the memory cell is programmed utilizing a programming pulse that reverse biases the diode thereof.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: November 18, 2008
    Assignee: Sandisk 3D LLC
    Inventor: James M. Cleeves
  • Optimization of critical dimensions and pitch of patterned features in and above a substrate
    Patent number: 7423304
    Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: September 9, 2008
    Assignee: Sandisck 3D LLC
    Inventors: James M. Cleeves, Roy E. Scheuerlein
  • Electrically isolated pillars in active devices
    Patent number: 7413945
    Abstract: A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 19, 2008
    Assignee: SanDisk 3D LLC
    Inventors: Michael A. Vyvoda, Manish Bhatia, James M. Cleeves, N. Johan Knall
  • VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION
    Publication number: 20080119027
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 22, 2008
    Inventors: Vivek Subramanian, James M. Cleeves
  • INTERNAL COMBUSTION ENGINE
    Publication number: 20080047530
    Abstract: An internal combustion engine is provided. Facing pistons eliminate a cylinder head, thereby reducing heat losses through a cylinder head. Facing pistons also halve the stroke that would be required for one piston to provide the same compression ratio, and the engine can thus be run at higher revolutions per minute and produce more power. An internal sleeve valve is provided for space and other considerations. A combustion chamber size-varying mechanism allows for adjustment of the minimum size of an internal volume to increase efficiency at partial-power operation. Variable intake valve operation is used to control engine power.
    Type: Application
    Filed: April 2, 2007
    Publication date: February 28, 2008
    Inventor: James M. Cleeves
  • Vertically stacked field programmable nonvolatile memory and method of fabrication
    Patent number: 7319053
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: January 15, 2008
    Assignee: SanDisk 3D LLC
    Inventors: Vivek Subramanian, James M. Cleeves
  • Spark plug
    Patent number: 7309951
    Abstract: A spark plug is disclosed having at least one main electrode and at least one secondary electrode. The gaps associated with the secondary electrodes are between one third and two thirds the optimum gap distance. Resistors associated with the secondary electrodes control the current flow and therefore the voltage on the electrodes.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 18, 2007
    Inventor: James M. Cleeves
  • Post vertical interconnects formed with silicide etch stop and method of making
    Patent number: 7307012
    Abstract: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present invention can be substantially the same as the minimum feature size, even at very small minimum feature size.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: December 11, 2007
    Assignee: Sandisk 3D LLC
    Inventor: James M. Cleeves
  • Vertically stacked field programmable nonvolatile memory and method of fabrication
    Patent number: 7265000
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: September 4, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Vivek Subramanian, James M. Cleeves
  • Electrically isolated pillars in active devices
    Patent number: 7245000
    Abstract: A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: July 17, 2007
    Assignee: SanDisk Corporation
    Inventors: Michael A. Vyvoda, Manish Bhatia, James M. Cleeves, N. Johan Knall
  • Method of uniform seeding to control grain and defect density of crystallized silicon for use in sub-micron thin film transistors
    Patent number: 7195992
    Abstract: A method to create a polysilicon layer with large grains and uniform grain density is described. A first amorphous silicon layer is formed. A crystallizing agent is selectively introduced in a substantially symmetric pattern, preferably symmetric in two dimensions, across an area of the first amorphous layer. The crystallizing agent may be, for example, silicon nuclei, germanium, or laser energy. A mask layer is formed on the amorphous silicon layer, and holes etched in the mask layer in a symmetric pattern to expose the amorphous layer to, for example, silicon nuclei or germanium) only in the holes. The mask layer is removed and a second amorphous layer formed on the first. If laser energy is used, no mask layer or second amorphous layer is generally used. The wafer is annealed to form a polysilicon layer with substantially no amorphous silicon remaining between the grains.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 27, 2007
    Assignee: Sandisk 3D LLC
    Inventors: Shuo Gu, James M. Cleeves
  • Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement
    Patent number: 7190602
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: March 13, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, James M. Cleeves
  • Vertically stacked field programmable nonvolatile memory and method of fabrication
    Patent number: 7160761
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: January 9, 2007
    Assignee: SanDisk 3D LLC
    Inventors: James M. Cleeves, Vivek Subramanian
  • System and method for recalibrating flat panel field emission displays
    Patent number: 7158102
    Abstract: A field emission display (FED) having a correction system with a correction coefficient derived from emission current is presented. Within one embodiment in accordance with the present invention, a field emission display has an anode at the faceplate and a focus structure. The anode potential is held at ground while the focus structure potential is held between, but is not limited to, 40 and 50 volts. The current flowing to the focus structure is measured and used as the basis for the correction coefficient for the field emission display.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: January 2, 2007
    Assignees: Candescent Technologies Corporation, Sony Corporation
    Inventors: Ronald L. Hansen, James C. Dunphy, Christopher J. Spindt, James M. Cleeves, Jerome M. Truppa, Gregory M. Fink, Yukinobu Iguchi
  • Vertically stacked field programmable nonvolatile memory and method of fabrication
    Patent number: 7157314
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: January 2, 2007
    Assignee: SanDisk Corporation
    Inventors: Vivek Subramanian, James M. Cleeves
  • Dense arrays and charge storage devices
    Patent number: 7129538
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: October 31, 2006
    Assignee: Sandisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul M. Farmwald, Brad Herner
  • Three-dimensional memory
    Patent number: 7115967
    Abstract: A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: October 3, 2006
    Assignee: Sandisk 3D LLC
    Inventor: James M. Cleeves
  • Spark plug
    Patent number: 7098581
    Abstract: A spark plug is disclosed having at least one main electrode and at least one secondary electrode. The gaps associated with the secondary electrodes are between one third and two thirds the optimum gap distance. Resistors associated with the secondary electrodes control the current flow and therefore the voltage on the electrodes.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 29, 2006
    Inventor: James M. Cleeves