Abstract: A shock absorbing and protective form of a horseshoe comprises a base that conforms to the shape of the perimeter of the horse's hoof, and from which protrudes a series of podded cleats that are strategically aligned and positioned below the horn of the hoof providing the prerequisite support for the horse. Each podded cleat has an internal air chamber, that when combined with the complying shape of the external wall allows partial or full collapse or deflation of this structural element effecting a most significant degree of cushioning, thus allowing a relatively high durometer elastomer for composition that would not otherwise provide sufficient compressibility, but having physical properties that surmount the factors of abrasion and wear and where such hard materials are identifiable as having a low frictional resistance in comparison to highly compressible, soft elastomers.

Abstract: A nailess horse shoe having a cup shaped configuration open at the rear part, molded of flexible plastics or polyurethyne material having a forwardly extending slot shaped opening in the bottom. A sponge rubber sole is provided on the lower surface on the bottom of the shoe and clamping or tightening members in the form of rod members extend between the lateral side walls and are provided with tightening nuts to draw the lateral side walls towards each other into clamping engagement onto the horse's hoof. A sock is insertable between the hoof and the inner surface of the shoe and a device for attaching weights is provided on the front of the shoe.

Abstract: An FET load gate compensator employing feedback to control the load gate voltage holds the circuit delay and power dissipation of an integrated circuit nearly constant. The integrated circuit chip is provided with several stages of inverters which act as a delay sensor to simulate the delay of the operational circuit on the chip. The time delay of the delay sensor on the integrated circuit chip is compared with an external clock reference by a delay comparator. The delay comparator generates an output voltage which is used to adjust the load gate voltage until the delay in the delay sensor is equal to the clock reference. Since the same load gate voltage is distributed in the rest of the operational circuits in the integrated circuit chip, the delay times of these circuits will track with that of the delay sensor and thus also tend to be held constant.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: disclosed is an apparatus for generating and controlling a desired substrate potential level or a semiconductor chip. A pulse source, such as an oscillator, provides a pulse train which, in combination with a control signal from the substrate voltage detector, selectively discharges a capacitor in a voltage level converter for obtaining a desired level of substrate potential. A feedback path through the substrate regulates the conductivity of a reference transistor in the substrate voltage detector providing the required control signal.