Patents by Inventor James M. Magee
James M. Magee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940931Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.Type: GrantFiled: January 5, 2021Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Patent number: 11860796Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: GrantFiled: August 9, 2021Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Jeremy C. Andrus, Joseph R. Auricchio, Russell A. Blaine, Daniel A. Chimene, Simon M. Douglas, Landon J. Fuller, Yevgen Goryachok, John K. Kim-Biggs, Arnold S. Liu, James M. Magee, Daniel A. Steffen, Roberto G. Yepez
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Patent number: 11579934Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: March 22, 2021Date of Patent: February 14, 2023Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
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Patent number: 11422857Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.Type: GrantFiled: May 22, 2020Date of Patent: August 23, 2022Assignee: Apple Inc.Inventors: Kushal Dalmia, Jeremy C. Andrus, Daniel A. Chimene, Nigel R. Gamble, James M. Magee, Daniel A. Steffen
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Publication number: 20210365389Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Jeremy C. ANDRUS, Joseph R. Auricchio, Russell A. BLAINE, Daniel A. CHIMENE, Simon M. DOUGLAS, Landon J. FULLER, Yevgen GORYACHOK, John K. KIM-BIGGS, Arnold S. LIU, James M. MAGEE, Daniel A. STEFFEN, Roberto G. YEPEZ
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Publication number: 20210318909Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: March 22, 2021Publication date: October 14, 2021Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
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Patent number: 11086800Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: GrantFiled: May 22, 2020Date of Patent: August 10, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, Joseph R. Auricchio, Russell A. Blaine, Daniel A. Chimene, Simon M. Douglas, Landon J. Fuller, Yevgen Goryachok, John K. Kim-Biggs, Arnold S. Liu, James M. Magee, Daniel A. Steffen, Roberto G. Yepez
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Patent number: 11080095Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: August 3, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Patent number: 11048562Abstract: Techniques are disclosed relating to efficiently handling execution of multiple threads to perform various actions. In some embodiments, an application instantiates a queue and a synchronization primitive. The queue maintains a set of work items to be operated on by a thread pool maintained by a kernel. The synchronization primitive controls access to the queue by a plurality of threads including threads of the thread pool. In such an embodiment, a first thread of the application enqueues a work item in the queue and issues a system call to the kernel to request that the kernel dispatch a thread of the thread pool to operate on the first work item. In various embodiments, the dispatched thread is executable to acquire the synchronization primitive, dequeue the work item, and operate on it.Type: GrantFiled: December 8, 2017Date of Patent: June 29, 2021Assignee: Apple Inc.Inventors: Daniel A. Steffen, Pierre Habouzit, Daniel A. Chimene, Jeremy C. Andrus, James M. Magee, Puja Gupta
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Publication number: 20210157748Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.Type: ApplicationFiled: January 5, 2021Publication date: May 27, 2021Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Patent number: 10956220Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: March 23, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
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Patent number: 10901920Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.Type: GrantFiled: April 10, 2019Date of Patent: January 26, 2021Assignee: Apple Inc.Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Patent number: 10884811Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: January 5, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Publication number: 20200379804Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Kushal Dalmia, Jeremy C. Andrus, Daniel A. Chimene, Nigel R. Gamble, James M. Magee, Daniel A. Steffen
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Publication number: 20200379925Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Jeremy C. Andrus, Joseph R. Auricchio, Russell A. Blaine, Daniel A. Chimene, Simon M. Douglas, Landon J. Fuller, Yevgen Goryachok, John K. Kim-Biggs, Arnold S. Liu, James M. Magee, Daniel A. Steffen, Roberto G. Yepez
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Patent number: 10671430Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.Type: GrantFiled: December 8, 2017Date of Patent: June 2, 2020Assignee: Apple Inc.Inventors: Daniel A. Steffen, Jainam A. Shah, James M. Magee, Jeremy C. Andrus, Russell A. Blaine
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Publication number: 20190370061Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.Type: ApplicationFiled: April 10, 2019Publication date: December 5, 2019Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Patent number: 10417054Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: September 17, 2019Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Patent number: 10310891Abstract: Disclosed herein are systems, methods, and computer-readable media directed to scheduling threads in a multi-processing environment that can resolve a priority inversion. Each thread has a scheduling state and a context. A scheduling state can include attributes such as a processing priority, classification (background, fixed priority, real-time), a quantum, scheduler decay, and a list of threads that may be waiting on the thread to make progress. A thread context can include registers, stack, other variables, and one or more mutex flags. A first thread can hold a resource with a mutex, the first thread having a low priority. A second thread having a scheduling state with a high priority can be waiting on the resource and may be blocked behind the mutex held by the first process. A scheduler can execute the context of the lower priority thread using the scheduler state of the second, higher priority thread. More than one thread can be waiting on the resource held by the first thread.Type: GrantFiled: September 30, 2015Date of Patent: June 4, 2019Assignee: Apple Inc.Inventors: Daniel A. Chimene, Daniel A. Steffen, James M Magee, Russell A. Blaine, Shantonu Sen
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Publication number: 20190155656Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.Type: ApplicationFiled: November 19, 2018Publication date: May 23, 2019Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, James M. Magee