Patents by Inventor James M. Magee
James M. Magee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180349175Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: January 12, 2018Publication date: December 6, 2018Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
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Publication number: 20180349186Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: January 12, 2018Publication date: December 6, 2018Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Publication number: 20180349209Abstract: Techniques are disclosed relating to efficiently handling execution of multiple threads to perform various actions. In some embodiments, an application instantiates a queue and a synchronization primitive. The queue maintains a set of work items to be operated on by a thread pool maintained by a kernel. The synchronization primitive controls access to the queue by a plurality of threads including threads of the thread pool. In such an embodiment, a first thread of the application enqueues a work item in the queue and issues a system call to the kernel to request that the kernel dispatch a thread of the thread pool to operate on the first work item. In various embodiments, the dispatched thread is executable to acquire the synchronization primitive, dequeue the work item, and operate on it.Type: ApplicationFiled: December 8, 2017Publication date: December 6, 2018Inventors: Daniel A. Steffen, Pierre Habouzit, Daniel A. Chimene, Jeremy C. Andrus, James M. Magee, Puja Gupta
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Publication number: 20180349182Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: January 12, 2018Publication date: December 6, 2018Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Publication number: 20180349176Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: January 12, 2018Publication date: December 6, 2018Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Publication number: 20180349181Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.Type: ApplicationFiled: December 8, 2017Publication date: December 6, 2018Inventors: Daniel A. Steffen, Jainam A. Shah, James M. Magee, Jeremy C. Andrus, Russell A. Blaine
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Patent number: 10140157Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.Type: GrantFiled: May 29, 2014Date of Patent: November 27, 2018Assignee: Apple Inc.Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, James M. Magee
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Publication number: 20160357600Abstract: Disclosed herein are systems, methods, and computer-readable media directed to scheduling threads in a multi-processing environment that can resolve a priority inversion. Each thread has a scheduling state and a context. A scheduling state can include attributes such as a processing priority, classification (background, fixed priority, real-time), a quantum, scheduler decay, and a list of threads that may be waiting on the thread to make progress. A thread context can include registers, stack, other variables, and one or more mutex flags. A first thread can hold a resource with a mutex, the first thread having a low priority. A second thread having a scheduling state with a high priority can be waiting on the resource and may be blocked behind the mutex held by the first process. A scheduler can execute the context of the lower priority thread using the scheduler state of the second, higher priority thread. More than one thread can be waiting on the resource held by the first thread.Type: ApplicationFiled: September 30, 2015Publication date: December 8, 2016Inventors: Daniel A. CHIMENE, Daniel A. STEFFEN, James M. MAGEE, Russell A. BLAINE, Shantonu SEN
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Patent number: 9286120Abstract: A method for resource management of a data processing system is described. According to one embodiment, a request is received via a programming interface from a program to modify a resource budget assigned to the program, where the resource budget specifies an amount of resources of the data processing system the program can utilize during an execution of the program. It is determined whether the program is entitled to modify the resource budget based on entitlement associated with the program. The resource budget for the program is modified if it is determined the program is entitled to modify the resource budget and the modified resource budget is enforced against the program during the execution of the program.Type: GrantFiled: August 30, 2012Date of Patent: March 15, 2016Assignee: Apple Inc.Inventors: James M. Magee, Russell A. Blaine, Umesh S. Vaishampayan
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Publication number: 20150347192Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Applicant: Apple Inc.Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, James M. Magee
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Publication number: 20130332936Abstract: A method for resource management of a data processing system is described. According to one embodiment, a request is received via a programming interface from a program to modify a resource budget assigned to the program, where the resource budget specifies an amount of resources of the data processing system the program can utilize during an execution of the program. It is determined whether the program is entitled to modify the resource budget based on entitlement associated with the program. The resource budget for the program is modified if it is determined the program is entitled to modify the resource budget and the modified resource budget is enforced against the program during the execution of the program.Type: ApplicationFiled: August 30, 2012Publication date: December 12, 2013Inventors: James M. Magee, Russell A. Blaine, Umesh S. Vaishampayan
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Patent number: 8516198Abstract: A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software.Type: GrantFiled: October 21, 2010Date of Patent: August 20, 2013Assignee: Apple Inc.Inventors: Matt Watson, James M. Magee
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Patent number: 8392925Abstract: A method and apparatus which maintain a plurality of counters to synchronize a plurality of requests for a lock independent of interlocks. The plurality of counters include a lock counter and an unlock counter. The requests wait in a wait queue maintained separately from the counters without direct access between the counters and the wait queue. The lock counter indicates a cumulative number of lock requests to acquire the lock. The unlock counter indicates a cumulative number of unlock requests to release the lock acquired. One or more requests waiting for the lock are selected according to the counters to be granted with the lock when the lock is released. A request corresponds to a task performing synchronized operations when granted with the lock.Type: GrantFiled: March 26, 2009Date of Patent: March 5, 2013Assignee: Apple Inc.Inventors: Ananthakrishna Ramesh, James M. Magee
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Publication number: 20110035554Abstract: A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software.Type: ApplicationFiled: October 21, 2010Publication date: February 10, 2011Inventors: Matt Watson, James M. Magee
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Patent number: 7827358Abstract: A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software.Type: GrantFiled: January 7, 2007Date of Patent: November 2, 2010Assignee: Apple Inc.Inventors: Matt Watson, James M. Magee
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Publication number: 20100250809Abstract: A method and apparatus to maintain a plurality of counters to synchronize a plurality of requests for a lock independent of interlocks are described. The plurality of counters include a lock counter and an unlock counter. The requests wait in a wait queue maintained separately from the counters without direct access between the counters and the wait queue. The lock counter indicates a cumulative number of lock requests to acquire the lock. The unlock counter indicates a cumulative number of unlock requests to release the lock acquired. One or more requests waiting for the lock are selected according to the counters to be granted with the lock when the lock is released. A request corresponds to a task performing synchronized operations when granted with the lock.Type: ApplicationFiled: March 26, 2009Publication date: September 30, 2010Inventors: ANANTHAKRISHNA RAMESH, JAMES M. MAGEE
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Publication number: 20080168235Abstract: A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software.Type: ApplicationFiled: January 7, 2007Publication date: July 10, 2008Inventors: Matt Watson, James M. Magee
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Patent number: 6543737Abstract: A holding device for temporarily attaching a facial tissue box or similar container to a supporting structure such as glove box door, sun visor, window, bed railing or headboard, or similar. The device is removably attachable to both the box and the supporting structure. Two laterally projecting arms grip the box while a clip attaches to the structure. The arms may comprise hooks, points or other features designed to enhance their grip on a paperboard, or similar, box. These features may optionally penetrate, crimp, or depress the side of the container. If desired, one or both of the arms may be adjustable to accommodate a range of box widths and/or depths.Type: GrantFiled: July 30, 2001Date of Patent: April 8, 2003Inventors: Clayton O. Decker, James M. Magee
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Publication number: 20020113187Abstract: A holding device for temporarily attaching a facial tissue box or similar container to a supporting structure such as glove box door, sun visor, window, bed railing or headboard, or similar. The device is removably attachable to both the box and the supporting structure. Two laterally projecting arms grip the box while a clip attaches to the structure. The arms may comprise hooks, points or other features designed to enhance their grip on a paperboard, or similar, box. These features may optionally penetrate, crimp, or depress the side of the container. If desired, one or both of the arms may be adjustable to accommodate a range of box widths and/or depths.Type: ApplicationFiled: July 30, 2001Publication date: August 22, 2002Inventors: Clayton O. Decker, James M. Magee
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Patent number: 6394329Abstract: A holder for a water, beverage, or similar container which attaches the container to the user's belt. An upright portion of the holder is designed to be inserted behind the user's belt while a lateral projection supports and retains the container. Two openings in the lateral projection have different sizes: the first allows for easy insertion and removal of the neck, or top, of the container; and the second closely matches the size of the container neck and prevents it from being removed vertically. A reduced sized passage provides for movement of the container between the two openings and is sized to resist this movement, but not prevent it. Alternative embodiments of the holder incorporate devices to retain the holder on the user's belt, and or to retain the bottle within the holder.Type: GrantFiled: September 19, 2000Date of Patent: May 28, 2002Inventor: James M. Magee