Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: Methods and data processing systems are provided to share a common pin between two circuits in microcontroller unit (MCU). Signals are received at a common pin included in the MCU. If the first circuit has been enabled, then the received signals are analyzed to determine whether the signals are valid command signals for the first circuit. If the signals are not a valid command signal, then a second circuit is performed. If the first circuit has not been enabled, then an alternate function is performed. One of the operations performed by the alternate function is to determine whether to enable the first function. In one embodiment, the first circuit is a background debug controller of the MCU and the second circuit is a reset circuit.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: A method and apparatus for updating a count value is provided. The count value includes a first portion stored in a non-volatile memory and a second portion stored in a volatile memory. The second portion of the count value is updated upon elapse of a period of time. The first portion of the count value is updated if the second portion of the count value overflowed and a use indicator corresponding to the first portion of the count value is set. The first portion of the count value is also updated if a power on reset event is detected and a use indicator corresponding to the first portion of the count value is set.

Abstract: A method is provided for secure communication between a transmitter and a receiver. The transmitter comprises a non-volatile memory for storing a first portion of a count value, where the count value is updated after an elapse of a period of time. The transmitter comprises a volatile memory for storing a second portion of the count value. In response to receipt of a transmit request, the transmitter sets a use indicator corresponding to the first portion of the count value. Upon elapse of the period of time, the second portion of the count value is updated. The first portion of the count value is updated if the second portion of the count value overflows and if the use indicator corresponding to the first portion set. A message authentication code is generated based on at least the count value. A message transmitted to the receiver comprises at least the message authentication code.

Abstract: Methods and data processing systems are provided to share a common pin between two circuits in microcontroller unit (MCU). Signals are received at a common pin included in the MCU. If the first circuit has been enabled, then the received signals are analyzed to determine whether the signals are valid command signals for the first circuit. If the signals are not a valid command signal, then a second circuit is performed. If the first circuit has not been enabled, then an alternate function is performed. One of the operations performed by the alternate function is to determine whether to enable the first function. In one embodiment, the first circuit is a background debug controller of the MCU and the second circuit is a reset circuit.

Abstract: A data processing system (10) has an embedded non-volatile memory (22) that is programmed and erased by use of a high voltage provided by a charge pump (78). In order to prevent the non-volatile memory (22) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump (78) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit (110) in response to a program or erase operation being initiated. A control register (76) will provide a high voltage enable signal to the charge pump (78) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit (110) may be enabled by another condition to protect the data processing system (10) from an authorized access.

Abstract: A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.

Abstract: Embodiments of the present invention relate to a mechanism to prevent the oscillator from being stopped when a host development system is coupled to the background debug communications interface and the background debug mode has been enabled. This allows background debugging operations to continue when the target data processing system is in a low power mode. Other embodiments relate to a mechanism for allowing a host development system to request a synchronization timing pulse from a target data processing system so the correct clock speed can be determined for background communications. Alternate embodiments relate to a data processing system having a system clock unit and a background debug system where the background debug system includes a background debug clock unit, separate from the system clock unit, and an enable control. When the enable control is asserted, the background debug clock unit is enabled, independent of the system clock unit.

Abstract: A debug module (20) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory (30) during program development. The debug information is provided to an external host via a serial communication interface (14) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Abstract: A debug module (20) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory (30) during program development. The debug information is provided to an external host via a serial communication interface (14) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Abstract: Embodiments of the present invention relate to a mechanism to prevent the oscillator from being stopped when a host development system is coupled to the background debug communications interface and the background debug mode has been enabled. This allows background debugging operations to continue when the target data processing system is in a low power mode. Other embodiments relate to a mechanism for allowing a host development system to request a synchronization timing pulse from a target data processing system so the correct clock speed can be determined for background communications. Alternate embodiments relate to a data processing system having a system clock unit and a background debug system where the background debug system includes a background debug clock unit, separate from the system clock unit, and an enable control. When the enable control is asserted, the background debug clock unit is enabled, independent of the system clock unit.

Abstract: A method for automatically detecting a programmed status of a non-volatile memory and selecting one of multiple operational modes based on that status. In one embodiment a non-volatile memory (102) has a normal and an access restricted operational mode. The memory is placed in the access restricted operational mode once it is programmed in order to prevent unauthorized access to the programmed data. A detection logic (226) determines whether the non-volatile memory is in a non-programmed state. Based on this detection it is determined whether the non-volatile memory is to be placed in a normal or an access restricted operational mode. The invention relates also to determining an operational mode of the microcontroller which can advantageously be incorporated into an assembled electronic device.

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.

Abstract: A communication system (5) provides an improved wired-OR connection for use in the bidirectional communication of information between two devices. A first device is a master host device (10) which initiates all communications while one or more slave devices (40) connected to a wired-OR common communication line either receive information from or send information to the master device. Depending on a direction of a data transfer operation, either the master or the host determines a bit time required to perform the data transfer. Furthermore, a device which terminates the bit time is the device which issues a speed up pulse for driving the common communication line to a logic one value. Such speed up pulses permit faster communication than is normally possible on a wired-OR communication line and makes high speed bidirectional communication over a single wired-OR line practical.

Abstract: A circuit (14) to evaluate a plurality of fuzzy logic rules as executable instructions in a data processor (310). A first instruction retrieves a fuzzy input value from memory (32) and stores it in an accumulator (58). A second instruction retrieves a second fuzzy input value from memory (32) and compares it to the fuzzy input value stored in the accumulator (58). The minimum value of the two fuzzy input values is then allowed to remain in the accumulator (58). Another program instruction retrieves a fuzzy output value from memory (32) and compares it to the value in the accumulator (58). The maximum of these two values is then determined by the instruction and this maximum value is then stored in memory (32).

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.

Abstract: In a data processing system (10) implementing a fuzzy logic operation, a switching mechanism (802) is implemented to provide a selection between a variable format rule base (803) and a fixed format rule base. The variable format rule base utilizes buffers between fuzzy input addresses and fuzzy output addresses, while the fixed format rule base does not require such buffers since a number of fuzzy input addresses and fuzzy output addresses is predetermined.