Abstract: A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). The queue controller generally includes a register (52, 62) which indicates an address to be accessed and a direction control signal. Additionally, each peripheral device has a queue control register which is configured to access a selected channel of the queue memory. The queue memory system described herein also efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. For example, the queue memory system will wait (for up to thirty-two timing cycles) for a timing cycle in which the central processing unit does not require use of a bus.

Abstract: The data processing system(10) implements a resumable instruction using two instruction bytes. When a program counter (72) points to a first instruction byte, a first data processing operation is initiated. If an interrupt occurs during execution of the first data processing operation, intermediate data calculations held in a plurality of temporary registers (64, 66, 68) are saved in stack memory at a location pointed to by the stack pointer register (72). The program counter is incremented to point to a second byte of the instruction. An instruction resume operation is executed and the intermediate results of the data processing operation are accessed from the stack memory and restored to respective storage locations within the data processing system. After the intermediate results are restored, the program counter is decremented to point to the first instruction byte and the instruction continues executing the data processing operation as though no interrupt occurred.

Abstract: An improved internal memory address mapping apparatus repositions a lower priority memory resource when two or more memory resources are located at the same address space. Upon receipt of a signal indicating that two memory resources have been mapped to the same address space, an internal address mapping decoder assigns the conflicting portion of the memory resource with the lower priority a different address range. The portion of the memory resource with the lower priority not conflicting with another memory resource is accessed without being repositioned. This internal memory address mapping apparatus assures that all portions of conflicting memory resources remain accessible to the user.

Abstract: A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.

Abstract: A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

Abstract: A data processor with memory within a single integrated circuit package provides a programmable "secure mode" of operation to selectively restrict access and protect information stored in its memory. The secure mode of operation is included in addition to a "single chip mode" wherein the data processor accesses both data and instructions strictly from within the single integrated circuit package. An "expanded mode" of operation also exists wherein the data processor may access either internal or external memory for both instructions and data. The secure mode of operation restricts accesses of instructions to memory contained within the single integrated circuit while allowing data accesses to memory either internal or external to the integrated circuit. The secure mode is accomplished by selectively isolating internal data/instruction bus transfer activity from an external data/instruction bus.

Abstract: A microcomputer with an external bus interface for providing communication with external peripheral devices such as memory and the like is provided with on-board chip select logic and programmable bus stretching capability. The chip select logic provides chip select signals to external devices when addresses fall within pre-selected ranges, eliminating the "glue" logic normally required for this purpose. The programmable bus stretching feature inserts a pre-selected number of "wait states" into any external bus cycle for which it is programmed by stretching, or freezing, the central processing unit and external bus interface unit clocks. Other internal clocks, such as those which drive timers and/or serial interface baud rate generators are not frozen by the bus stretch.

Abstract: A data processor and method includes a timer system for producing a first output compare signal when a counter value equals a compare value. A register alternatively produces a second output compare signal in response to having a given bit value written therein. Logic circuitry provides an output compare function in response to either the first or the second output compare signals.

Abstract: A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. The starting address registers, and enable registers which control whether each patch block is placed in the memory map, are programmable under control of the microcomputer's CPU. Newly programmed values in these registers are not effective to alter the memory map until a reset sequence enables a latch. In particular embodiments, patch blocks may overlie mask ROM, internal EPROM and/or EEPROM, external memory or devices or any other desireable portion of the memory map.

Abstract: In a microcomputer, an address mapper allows the user to selectively map a resource which is ordinarily addressable in one portion of the address range of the microcomputer into a correspondingly sized area elsewhere in the address range. Using a resource map address stored by the user in an addressable map register, the mapper continuously compares the map address to a corresponding number of bits on the microcomputer's address bus. When a match is detected, the mapper enables the address decoder of the mapped resource. The mapper can also map the map register. Since the mapper can map more than one resource, an interlock mechanism resolves access conflicts.

Abstract: An output compare system and method for automatically controlling multiple outputs in a data processor includes an output compare mask register for holding a set bit therein. An output compare data register is coupled to a control output of the output compare mask register for holding a data bit therein. Apparatus for initiating an output compare function are coupled to a control input to the output compare mask register whereby the data bit will be transferred to an output of the data processor if the set bit is present. The system and method allow for simultaneous utilization of multiple output compare functions to achieve one-cycle-wide pulses on a timer output pin.

Abstract: A data processor having an integral timer including a clock generator producing a specific frequency output comprises a counter chain having an input and output thereof for supplying a fixed frequency divide function. A programmable prescaler couples the clock generator output to the counter chain input for providing a predetermined divisor input to the counter chain. A postscaler operates in consonance with the programmable prescaler coupled to the counter chain output for providing a timer output compensated for the predetermined divisor input. In operation, the timer output has a frequency bearing a constant relationship to the clock generator output frequency independent of the predetermined divisor input of the programmable prescaler.

Abstract: A write protection circuit for a control register includes a first logic circuit which provides a write enable signal to the control register in response to simultaneously receiving a register select signal, a write control signal and an enable signal. A second logic circuit provides the enable signal to the first logic circuit only until the first logic circuit first provides the write enable signal. The second logic circuit will also cease to provide the enable signal in response to a time-out signal. In response to either a reset signal or a test signal, the second logic circuit will again provide the enable signal.