Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract: An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.

Abstract: According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.

Abstract: Approaches for protecting design information are disclosed. In one approach, a request for an IP core from an integrated circuit device is received, and the request includes identification information. An identifier range is determined from the identification information. The identifier range includes a plurality of unique device identifiers identifying a plurality of integrated circuit devices that are allowed to receive the IP core. The identifier range is downloaded to the integrated circuit device, which evaluates whether or not a unique device identifier that is stored on the integrated circuit device is within the downloaded identifier range. The IP core is programmed into the integrated circuit in response to the unique device identifier that is stored on the integrated circuit device being within the downloaded identifier range.

Abstract: Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

Abstract: A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.

Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.

Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.

Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Abstract: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.

Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.