Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.

Abstract: Embedded logic circuits in combination with a configurable logic resources on a common integrated circuit facilitates over-clocked operation of embedded, dual-port memory blocks. The implementation yields fully independent and simultaneous read/write access to the dual-port memory blocks from the configurable logic on each clock cycle of the configurable logic. Error detection/correction and data scrubbing is also facilitated by the embedded logic circuits, such that error detection/correction is completely transparent to the configurable logic, while data scrubbing is performed with minimal degradation to the memory access bandwidth of the configurable logic.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.

Abstract: A method and system for maintaining the security of design information is disclosed. The method includes generating an encrypted IP core by encrypting an IP core using a public key, downloading the encrypted IP core to a programmable logic device (PLD), and recovering the IP core by decrypting the encrypted IP core using a private key. The private key is associated with the PLD, and the public key and the private key correspond to one another. The method may further include the PLD receiving authorization information corresponding to the IP core and comparing local authorization information stored at the PLD with the authorization information.

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Abstract: Circuits and methods of concatenating first-in-first-out memory circuits (FIFOs). A concatenated FIFO includes first and second FIFOs. The data output terminals of the first FIFO are coupled to the data input terminals of the second FIFO. The read clock of the second FIFO is the system read clock, and the write clock of the first FIFO is the system write clock. Communication between the first and second FIFOs is controlled by the faster of the two system clocks. A control circuit coupled to both the first and second FIFOs has a local clock input terminal coupled to the read clock input terminal of the first FIFO and the write clock input terminal of the second FIFO. The control circuit is driven by status signals from the first and second FIFOs, and generates a read enable signal for the first FIFO and a write enable signal for the second FIFO.

Abstract: Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M?1) and 2(M?1)?1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.

Abstract: Methods of setting and/or resetting a lookup table (LUT) programmable to operate in shift register mode. The LUT is configured to operate as a shift register, and the final bit of the shift register is implemented using a memory element associated with the LUT. The shift register is reset (or set) by applying a reset (set) signal to the memory element, while providing a low (high) value from the memory element to a shift-in input terminal of the LUT; and shifting the low (high) value through the bits of the shift register. To perform this task, a write enable signal is provided that is independent from the reset (set) signal of the memory element and enables a shift clock signal. The shift clock signal is then repeatedly toggled to shift the low (high) value from the memory element successively through each bit of the shift register, while the value stored in the memory element is held constant by means of the independent reset (set) signal.

Abstract: A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

Abstract: Method and apparatus are described for determining when a convolution decoder is out of synchronization. Normalizations from a convolutional decoder are counted to provide a normalization count, and errors from the convolutional decoder are counted to provide an error count. One of the normalization count and the error count is compared to a first threshold associated with the selected one of the normalization count and the error count. The other of the normalization count and the error count is compared to a second threshold in response to meeting the first threshold, such as bit errors per X normalizations or normalizations per Y bit errors. From this latter comparison, an indicator is generated as to whether the convolutional decoder is synchronized or not.

Abstract: A method and apparatus for Time Division Duplex (TDD) synchronization of Access Points (APEs) uses the 1 pulse-per-second timing pulses of the Global Positioning System (GPS) and synchronization state machines for its Time Division Multiple Access (TDMA) structure. As a result, the present invention obviates the need for expensive voltage-controlled oscillators used by the prior art, and achieves stable timing accuracy within approximately 7.5 minutes, as opposed to the 12 to 24-hour period needed by prior art methods.

Abstract: Method and apparatus for concatenated and interleaved turbo product code (TPC) encoding and decoding are described. Described are series concatenated and interleaved TPC encoders and decoders. One or more combinations of these encoders and decoders may be combined to provide a coder/decoder (CODEC). Such a CODEC may be used for communicating information between a computer and a network via a data channel.

Abstract: Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

Abstract: Method and apparatus for data sampling is described. More particularly, a data sampling circuit having a delay line and a plurality of tap circuits is used to sample data and provide a vector indicative of a transition region of a sampled input signal. Additionally, a hybrid sampling circuit is described with a fine grain delay line and coarse grain delay lines. Furthermore, a controller is described for using such a vector to control which data samples are used.

Abstract: A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter.