Abstract: A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays. A data block is associated with each of the plurality of fluidic actuator arrays. The die includes an interface comprising a data pad and a clock pad, wherein a data bit value present at the data pad is loaded into a first data block corresponding to a first fluidic actuator array on a rising clock edge and loaded into a second data block corresponding to a second fluidic actuator array on a falling clock edge.

Abstract: A print component includes a plurality of data pads, a clock pad to receive an intermittent clock signal, and a plurality of actuator groups each corresponding to a different liquid type and to a different one of the data pads. Each actuator group includes a plurality of configuration functions, an array of fluid actuators, and an array of memory elements including a first portion corresponding to the plurality of configuration functions and a second portion corresponding to the array of fluid actuators. Each time the intermittent clock signal is present on the clock pad, the array of memory elements to serially load a segment of data bits from the corresponding data pad, including loading a first portion of data bits into the first portion of memory elements, and loading a second portion of data bits into the second portion of memory elements.

Abstract: A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays. A data block is associated with each of the plurality of fluidic actuator arrays. The die includes an interface comprising a data pad and a clock pad, wherein a data bit value present at the data pad is loaded into a first data block corresponding to a first fluidic actuator array on a rising clock edge and loaded into a second data block corresponding to a second fluidic actuator array on a falling clock edge.

Abstract: An integrated circuit includes a plurality of fluid actuation devices, a plurality of memory cells, a high-voltage high-power supply node, and a high-voltage low-power supply node. The high-voltage high-power supply node is to supply a first voltage and a first maximum current to the plurality of fluid actuation devices. The high-voltage low-power supply node is to supply a second voltage and a second maximum current to the plurality of memory cells.

Abstract: In an example, a logic circuit comprising a communications interface including a data contact to communicate via a communications bus, an enablement contact, separate from the communication interface, to receive an input to enable the logic circuit, and at least one memory register, comprising at least one reconfigurable address register. The logic circuit may be configured, such that, when enabled, it responds to communications sent via the communication bus which are addressed to the address held in a reconfigurable address register.

Abstract: A fluidic die including an array of fluid actuating devices addressable by a set of addresses, and an array of memory elements including a first portion to receive a first set of address bits representative of a first portion of an address of the set of addresses, and a second portion to receive a second set of address bits representative of a second portion of the address of the set of addresses. A first address driver is to provide a first portion of the address of the set of addresses based on the first set of address bits received by the first portion of memory elements, and a second address driver is to provide a remaining portion of the address of the set of addresses based on a second set of address bits received by the second portion of memory elements.

Abstract: An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.

Abstract: An integrated circuit includes a plurality of memory cells, an address decoder to select memory cells based on a data signal, activation logic to activate selected memory cells based on the data signal and a fire signal, and configuration logic to enable or disable access to the plurality of memory cells.

Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a strain gauge sensor, an amplifier, and a voltage bias generator. The strain gauge sensor generates a strain gauge signal. The amplifier amplifies the strain gauge signal. The voltage bias generator offsets the amplified strain gauge signal.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a status register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface, a data interface, and a fire interface. The control logic enables reading of the status register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface, and transitioning a signal on the fire interface to logic high with the signal on the single data interface floating.

Abstract: An integrated circuit includes a plurality of fluid actuation devices, a plurality of memory cells, a high-voltage high-power supply node, and a high-voltage low-power supply node. The high-voltage high-power supply node is to supply a first voltage and a first maximum current to the plurality of fluid actuation devices. The high-voltage low-power supply node is to supply a second voltage and a second maximum current to the plurality of memory cells.

Abstract: A print cartridge circuitry component comprising an integrated circuit for association with a plurality of fluid actuation devices and comprising input signal contacts to receive input signals from a host printer. The integrated circuit includes a plurality of memory cells, a first power supply node, and a second power supply node. The first power supply node is to supply power to the plurality of memory cells to write data to the plurality of memory cells. The second power supply node is to supply power to the plurality of memory cells to read data from the plurality of memory cells.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a digital circuit, an analog circuit, and control logic. The digital circuit outputs a digital signal to the interface. The analog circuit outputs an analog signal to the interface. The control logic activates the digital circuit or the analog circuit.

Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a digital circuit, an analog circuit, and control logic. The digital circuit outputs a digital signal to the interface. The analog circuit outputs an analog signal to the interface. The control logic activates the digital circuit or the analog circuit.

Abstract: An integrated circuit includes a plurality of memory cells, an address decoder to select memory cells based on a data signal, activation logic to activate selected memory cells based on the data signal and a fire signal, and configuration logic to enable or disable access to the plurality of memory cells.

Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.