Abstract: A seating arrangement includes an upwardly-extending back arrangement movable between an upright and reclined positions, and a seat arrangement that includes a first link member extending horizontally and having forward and rearward portions, a second link member spaced from the first link member, a third link member coupled to the first and second link members and substantially flexible along a majority of a length thereof, and a fourth link member operably coupled to the first and second link members, the fourth link member being substantially rigid along a majority of a length thereof, wherein the link members cooperate to form a linkage arrangement, and wherein the seat arrangement moves in a rearward direction as the back arrangement is moved between the upright position and the reclined position.

Abstract: A method and apparatus determines a physical location of a wireless infrastructure device. At least one coarse location data from an associated terminal device is determined. Additional coarse location data are stored and accumulated. The device location is considered accurate by determining that enough received coarse location data has been received.

Abstract: Methods and systems for accurately measuring and monitoring accumulated volume of hydraulic fluid in a blowout preventer (BOP) system, specifically for a function of interest, are disclosed. One method includes initializing a state machine algorithm, the state machine algorithm responsive to a BOP function of interest being activated; measuring an initial hydraulic flow rate baseline and an initial pressure baseline to create a hydraulic impedance variable for use in the state machine algorithm; monitoring an aggregate hydraulic flow rate and pressure of the BOP system over time; applying the hydraulic impedance variable to negate BOP system hydraulic flows not related to the BOP function of interest; and applying the state machine algorithm to determine when the BOP function of interest has been completed responsive to a total accumulated volume of hydraulic fluid.

Abstract: A wireless system for brain monitoring/mapping of neurological-disorder patients includes a plurality of electrodes each configured for surface abutment of brain tissue and main circuitry for placement outside a body of a patient and configured to transmit power at radio frequencies and send and receive data using infrared energy. Remote circuitry is provided for subcutaneous implantation in a head of the patient. The remote circuitry is connected to the plurality of electrodes and includes a multiplexer sampling signals from the plurality of electrodes. The multiplexer outputs electrode signals to an amplifier and A/D converter for transmission to the main circuitry. The remote circuitry is configured to (a) receive transmitted power at radio frequencies from the main circuitry, (b) capture and digitize full-bandwidth EEG signals from each of the electrodes, and (c) send data to and receive data from the main circuitry using infrared energy.

Abstract: A method and apparatus determines a physical location of a wireless infrastructure device. At least one coarse location data from an associated terminal device is determined. Additional coarse location data are stored and accumulated. The device location is considered accurate by determining that enough received coarse location data has been received.

Abstract: A method and apparatus determines a physical location of a wireless infrastructure device. At least one coarse location data from an associated terminal device is determined. Additional coarse location data are stored and accumulated. The device location is considered accurate by determining that enough received coarse location data has been received.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Abstract: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: Variable speed drive controlled discharge pumps are used for pumping chilled water from a chilled water storage tank to coils operatively associated with the air inlet of a gas turbine, wherein the gas turbine is used to generate electricity. Use of the variable speed drive controlled discharge pumps aids is protecting the temperature distribution in the chilled water storage tank so that a thermocline rises with the addition of chilled water during charging of the tank with chilled water, and lowers during discharge of the tank when using the chilled water to cool inlet air at one or more gas turbines operated at a facility.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A wireless system for brain monitoring/mapping of neurological-disorder patients includes a plurality of electrodes each configured for surface abutment of brain tissue and main circuitry for placement outside a body of a patient and configured to transmit power at radio frequencies and send and receive data using infrared energy. Remote circuitry is provided for subcutaneous implantation in a head of the patient. The remote circuitry is connected to the plurality of electrodes and includes a multiplexer sampling signals from the plurality of electrodes. The multiplexer outputs electrode signals to an amplifier and A/D converter for transmission to the main circuitry. The remote circuitry is configured to (a) receive transmitted power at radio frequencies from the main circuitry, (b) capture and digitize full-bandwidth EEG signals from each of the electrodes, and (c) send data to and receive data from the main circuitry using infrared energy.

Abstract: Analog electrical and pressure data obtained by an EEG/pressure sensor matrix from the subject are sent to a signal processing module that derives digital EEG data from the electrical signal and pressure data without using sensors attached to a subject's head. The pressure data are used as a secondary signal to measure the physical orientation of the subject's head. The physical orientation is used to transform the derived EEG signal to a known coordinate axis (the orientation of the subject's head) to obtain useful, consistent, and accurate EEG data. The EEG may be used to determine a sleep state of a subject and to awaken the subject while in a particular state.

Abstract: A wireless system for brain monitoring/mapping of neurological-disorder patients includes a plurality of electrodes each configured for surface abutment of brain tissue and main circuitry for placement outside a body of a patient and configured to transmit power at radio frequencies and send and receive data using infrared energy. Remote circuitry is provided for subcutaneous implantation in a head of the patient. The remote circuitry is connected to the plurality of electrodes and includes a multiplexer sampling signals from the plurality of electrodes. The multiplexer outputs electrode signals to an amplifier and A/D converter for transmission to the main circuitry. The remote circuitry is configured to (a) receive transmitted power at radio frequencies from the main circuitry, (b) capture and digitize full-bandwidth EEG signals from each of the electrodes, and (c) send data to and receive data from the main circuitry using infrared energy.

Abstract: Analog electrical and pressure data obtained by an EEG/pressure sensor matrix from the subject are sent to a signal processing module that derives digital EEG data from the electrical signal and pressure data without using sensors attached to a subject's head. The pressure data are used as a secondary signal to measure the physical orientation of the subject's head. The physical orientation is used to transform the derived EEG signal to a known coordinate axis (the orientation of the subject's head) to obtain useful, consistent, and accurate EEG data. The EEG may be used to determine a sleep state of a subject and to awaken the subject while in a particular state.

Abstract: The creation and implantation of an artificial nail in the treatment of deformed or missing nails includes preparing the nail bed. A polypropylene mesh is applied and anchored to the nail bed. Nail restoration material is applied to the polypropylene mesh. The nail restoration material is secured by regenerated nail tissue growing through the openings of the mesh whereby the mesh acts as an interface for the nail bed and the nail restoration material.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.