Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: A wireless system for brain monitoring/mapping of neurological-disorder patients includes a plurality of electrodes each configured for surface abutment of brain tissue and main circuitry for placement outside a body of a patient and configured to transmit power at radio frequencies and send and receive data using infrared energy. Remote circuitry is provided for subcutaneous implantation in a head of the patient. The remote circuitry is connected to the plurality of electrodes and includes a multiplexer sampling signals from the plurality of electrodes. The multiplexer outputs electrode signals to an amplifier and A/D converter for transmission to the main circuitry. The remote circuitry is configured to (a) receive transmitted power at radio frequencies from the main circuitry, (b) capture and digitize full-bandwidth EEG signals from each of the electrodes, and (c) send data to and receive data from the main circuitry using infrared energy.

Abstract: A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the flags.

Abstract: A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.

Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Abstract: A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect.

Abstract: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Abstract: A wireless system for monitoring a patient's brain tissue including (1) a plurality of electrodes abutting brain tissue, (2) main circuitry outside the patient's body to transmit power at radio frequencies and send/receive data using infrared energy, and (3) subcutaneously-implanted remote circuitry connected to the electrodes and configured to (a) receive transmitted RF power, (b) capture and digitize EEG signals from the electrodes, and (c) send/receive data to/from the main circuitry using IR energy, including sending digitized EEG signals from each electrode to capture the full bandwidth of each EEG signal. The system preferably includes circuitry to measure the electrical impedance of each electrode for real-time monitoring of the condition of the electrode/tissue interfaces to enhance interpretation of captured EEG signals.

Abstract: Red rust staining of Al/Zn coated steel strip in “acid rain” or “polluted” environments can be minimised by forming the coating as an Al—Zn—Si—Mg alloy coating with an OT:SDAS ratio greater than a value of 0.5:1, where OT is the overlay thickness on a surface of the strip and SDAS is the measure of the secondary dendrite arm spacing for the Al-rich alpha phase dendrites in the coating. Red rust staining in “acid rain” or “polluted” environments and corrosion at cut edges in marine environments can be minimised in Al—Zn—Si—Mg alloy coatings on steel strip by selection of the composition (principally Mg and Si) and solidification control (principally by cooling rate) and forming Mg2 Si phase particles of a particular morphology in interdendritic channels.

Abstract: A conferencing assembly for use with at least one computer, the assembly including a table top forming a table top opening, a leg support structure, a display screen supported adjacent the top surface, a switcher for controlling input to the display screen, a plurality of handsets, each hand set including a selector button usable to send a signal to the switcher thereby causing the switcher to link a computer associated with the selector button to the display, a plurality of handset cables, each handset cable having first and second ends linked to the switcher and an associated selector button, respectively, for passing signals from the selector buttons to the switcher, a take up assembly including a separate weight for each of the handset cables, the take up assembly disposed below the top member and aligned with the top opening, each handset cable linked to an associated weight, each weight applying a force tending to pull the second end of the associated handset cable into the opening.

Abstract: The creation and implantation of an artificial nail in the treatment of deformed or missing nails includes preparing the nail bed. A polypropylene mesh is applied and anchored to the nail bed. Nail restoration material is applied to the polypropylene mesh. The nail restoration material is secured by regenerated nail tissue growing through the openings of the mesh whereby the mesh acts as an interface for the nail bed and the nail restoration material.

Abstract: The creation and implantation of an artificial nail in the treatment of deformed or missing nails includes preparing the nail bed. A polypropylene mesh is applied and anchored to the nail bed. KeryFlex is applied to the polypropylene mesh.

Abstract: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.

Abstract: A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.

Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the flags.

Abstract: A method for coating a metal substrate, such as a steel strip, is disclosed. The method comprises vapour or electro-depositing an alloy control material, as described herein, onto the substrate and passing the substrate through a bath of molten coating material and forming a coating of the coating material onto the deposited alloy control material.

Abstract: A generator is disclosed. The generator comprising at least one layer, the at least one layer defining a cavity and at least one aperture, at least a portion of the at least one layer including a reflective medium, or coatings, the cavity configured to hold a fluid, a fluid inlet coupled to the at least one layer, the fluid inlet in fluid communication with the cavity, and a fluid outlet coupled to the at least one layer, the fluid outlet in fluid communication with the cavity, the fluid configured to absorb radiation, the fluid outlet configured to release the fluid to perform work.

Abstract: A conferencing assembly for use with at least one computer, the assembly including a table top forming a table top opening, a leg support structure, a display screen supported adjacent the top surface, a switcher for controlling input to the display screen, a plurality of handsets, each hand set including a selector button usable to send a signal to the switcher thereby causing the switcher to link a computer associated with the selector button to the display, a plurality of handset cables, each handset cable having first and second ends linked to the switcher and an associated selector button, respectively, for passing signals from the selector buttons to the switcher, a take up assembly including a separate weight for each of the handset cables, the take up assembly disposed below the top member and aligned with the top opening, each handset cable linked to an associated weight, each weight applying a force tending to pull the second end of the associated handset cable into the opening.