Patents by Inventor James P. Di Sarro
James P. Di Sarro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9575115Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device.Type: GrantFiled: October 11, 2012Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Nathaniel R. Chadwick, James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Kirk D. Peterson, Andrew A. Turner
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Patent number: 9536870Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.Type: GrantFiled: December 22, 2015Date of Patent: January 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 9413169Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.Type: GrantFiled: April 2, 2014Date of Patent: August 9, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 9377496Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.Type: GrantFiled: September 30, 2015Date of Patent: June 28, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr.
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Publication number: 20160111414Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.Type: ApplicationFiled: December 22, 2015Publication date: April 21, 2016Inventors: James P. DI SARRO, Robert J. GAUTHIER, Tom C. LEE, Junjun LI, Souvick MITRA, Christopher S. PUTNAM
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Patent number: 9274155Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.Type: GrantFiled: September 25, 2012Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr.
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Patent number: 9263402Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.Type: GrantFiled: November 26, 2014Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
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Publication number: 20160018452Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.Type: ApplicationFiled: September 30, 2015Publication date: January 21, 2016Inventors: Shunhua T. CHANG, James P. DI SARRO, Robert J. GAUTHIER, JR.
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Patent number: 9240471Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.Type: GrantFiled: August 28, 2013Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 9219055Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.Type: GrantFiled: June 14, 2012Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Nathan D. Jack, Jun Jun Li, Souvick Mitra
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Publication number: 20150363539Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.Type: ApplicationFiled: August 17, 2015Publication date: December 17, 2015Inventors: James P. Di Sarro, Robert J. Gauthier, Nathan D. Jack, JunJun Li, Souvick Mitra
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Publication number: 20150364914Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.Type: ApplicationFiled: August 17, 2015Publication date: December 17, 2015Inventors: James P. Di Sarro, Robert J. Gauthier, Nathan D. Jack, JunJun Li, Souvick Mitra
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Publication number: 20150288174Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 9064786Abstract: Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction.Type: GrantFiled: March 14, 2013Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 9059198Abstract: Fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.Type: GrantFiled: September 22, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
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Publication number: 20150115364Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.Type: ApplicationFiled: November 26, 2014Publication date: April 30, 2015Inventors: James P. Di Sarro, Robert J. Gauthier, JR., Junjun Li
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Patent number: 9006783Abstract: Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.Type: GrantFiled: June 5, 2014Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Chengwen Pei, Christopher S. Putnam, Theodorus E. Standaert
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Patent number: 8987073Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.Type: GrantFiled: July 11, 2012Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
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Publication number: 20150060939Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James P. DI SARRO, Robert J. GAUTHIER, JR., Tom C. LEE, Junjun LI, Souvick MITRA, Christopher S. PUTNAM
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Publication number: 20150050784Abstract: Fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.Type: ApplicationFiled: September 22, 2014Publication date: February 19, 2015Inventors: James P. Di Sarro, Robert J. Gauthier, JR., Junjun Li