Patents by Inventor James P. Held

James P. Held has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190058696
    Abstract: Techniques for sharing private data objects in a trusted execution environment using a distributed ledger are described. The techniques described herein may enable sharing of data objects, referred to herein as private data objects (PDOs), between individuals and organizations with access and update policies mediated by execution of code (referred to herein as a “smart contract”) carried with the PDO in a secure enclave. A distributed ledger may serve as a “public commit log” to ensure that there is a single, authoritative instance of the object and provide a means of guaranteeing atomicity of updates across interacting objects.
    Type: Application
    Filed: September 29, 2017
    Publication date: February 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Mic Bowman, Andrea Miele, James P. Held, Anand Rajan
  • Publication number: 20180145836
    Abstract: An automated method to verify a block record for a digital ledger involves a first validation node (FVN) which receives a block record from a second validation node (SVN). The block record comprises a digital signature for the block record. In response to receiving the block record, the FVN automatically obtains a node identifier for the SVN, based on the digital signature for the block record. The first validator node uses the node identifier for the SVN to determine whether the SVN belongs to a validation group that comprises the FVN. The FVN uses an attestation service to determine whether the node identifier for the SVN belongs to a node with a trusted processor. The FVN determines whether the digital signature for the block record was created with a private key that corresponds to the node identifier for the SVN. Other embodiments are described and claimed.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Applicant: Intel Corporation
    Inventors: Karla Saur, Mic Bowman, Andrea Miele, James P. Held
  • Patent number: 9747118
    Abstract: Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Richard L. Maliszewski, James P. Held, Daniel Baumberger
  • Patent number: 9588771
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
  • Publication number: 20170010895
    Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Hong Wang, John P. Shen, Edward T. Grochowski, Richard A. Hankins, Gautham N. Chinya, Bryant E. Bigbee, Shivnandan D. Kaushik, Xiang Chris Zou, Per Hammarlund, Scott Dion Rodgers, Xinmin Tian, Anil Aggarwal, Prashant Sethi, Baiju V. Patel, James P. Held
  • Publication number: 20160379212
    Abstract: In one embodiment, an apparatus includes a calculation logic to receive a plurality of wait certificates, each associated with a validated block of transactions of a distributed ledger system, and to generate a local mean value based thereon; a timer generation logic to generate a wait time for a proof of wait associated with a first block of transactions of the distributed ledger system based at least in part on the local mean value; a timer logic to identify when the wait period has expired; and a certificate generation logic to generate a wait certificate for the first block of transactions responsive to expiration of the wait period, the wait certificate to validate the first block of transactions. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Mic Bowman, James P. Held, Jesse Walker
  • Patent number: 9459874
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
  • Patent number: 9442721
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Colins, James P. Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20160019067
    Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
    Type: Application
    Filed: September 26, 2015
    Publication date: January 21, 2016
    Inventors: Hong Wang, John P. Shen, Edward T. Grochowski, Richard A. Hankins, Gautham N. Chinya, Bryant E. Bigbee, Shivnandan D. Kaushik, Xiang Chris Zou, Per Hammarlund, Scott Dion Rodgers, Xinmin Tian, Anil Aggawal, Prashant Sethi, Baiju V. Patel, James P Held
  • Patent number: 9189230
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James P. Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 9015455
    Abstract: A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: James P. Held, Scott H. Robinson, Vincent J. Zimmer
  • Patent number: 9003164
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Publication number: 20150070368
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Application
    Filed: November 14, 2014
    Publication date: March 12, 2015
    Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
  • Patent number: 8914618
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
  • Publication number: 20140208042
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Patent number: 8719547
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 6, 2014
    Assignee: Intel Corporation
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Patent number: 8521969
    Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers, James P. Held, Bill Alexander, Larry O. Smith, Scott H. Robinson, Sham M. Datta
  • Publication number: 20130205122
    Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
    Type: Application
    Filed: March 8, 2013
    Publication date: August 8, 2013
    Inventors: Hong WANG, John SHEN, Hong JIANG, Richard HANKINS, Per HAMMARLUND, Dion RODGERS, Gautham CHINYA, Baiju PATEL, Shiv KAUSHIK, Bryant BIGBEE, Gad SHEAFFER, Yoav Talgam, Yuval YOSEF, James P. HELD
  • Publication number: 20130013905
    Abstract: A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: James P. Held, Scott H. Robinson, Vincent J. Zimmer
  • Publication number: 20110072234
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley