Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract: A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi-core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.

Abstract: Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.

Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

Abstract: A method and apparatus pertaining to annotating a document window on a display device of a computer-based system. An annotation window is displayed over a selected portion of the document window where the annotation window is defined by a transparent window area bounded by a border. The annotation window enables the selected portion of the document window to be visible through the annotation window. Annotations are displayed within the annotation window where the annotations have a transparent background enabling the selected portion of the document windows to be visible through the transparent background of the annotations. When the annotation window is closed, the annotations are embedded into a contained document shown in the document window so that the annotations and the document are visible simultaneously in the selected portion of the document window.

Abstract: A debugger that is multi-task aware and capable of providing symbolic support to a graphical user interface (GUI) is disclosed. The debugger disclosed communicates with a multi-tasking kernel nested within a driver of the operating system within the 0 privilege level. The multi-tasking kernel distinguishes among the rest of its environment where a graphical user interface executes the driver tasks being debugged. The multi-tasking kernel, in cooperation with the debugger runs each element on a different thread of the same machine, thereby allowing the debugger and the driver tasks being debugged to continue to run without stopping operation of either the graphical user interface or the operating system associated with the graphical user interface.

Abstract: A method and apparatus for re-drawing a transparent window on at least one display device of a computer based system having a central processor and a memory is disclosed. Having a transparent window and an underlying second window, it is determined whether the underlying second window is active. If the underlying second window is active, the transparent window is hidden. The underlying second window is re-drawn and the transparent window is shown. Otherwise, the transparent window is maintained.

Abstract: A method and apparatus for relating (called hyperlinking) a region of one document to one or more regions of other documents. This is provided by using a mechanism for linking and embedding objects to establish the endpoints of the hyperlinks (called anchors) together with the creation of intermediate tables which maintain information about relations between regions of documents and attributes of the relationship. When a user selects a region in a document which participates in a relationship, a database program is invoked which displays information about related regions in other documents which may be accessed through the intermediate tables. An auxiliary table maintains information about attributes which may be custom designed by the user, such as author, date of creation, etc. The intermediate tables allow relationships among multiple regions of documents created by different applications.

Abstract: A method and apparatus creates and plays objects and sound synchronously after eliminating the silent segments of the sound. The method inserts sequence marks into the object and sound data, deletes silent segments of the sound data including the sequence marks that reside in the silent segments, and re-inserts the last deleted sequence mark back into the sound data. In so doing, the system detects the silent segments of the recorded sound stream data and deletes the silent portions from the recorded data. Upon replay of an object and its associated sound, any drawing done during the silent segments are played at the computer's full graphics drawing speed, only slowing down to real-time again when more sounds are encountered. Thus, the system plays "fast while silent" and slows to real-time when sounds are played. This saves the space required to stored the recorded sound, and the user does not have to wait through the silent periods.