Abstract: The invention relates to high affinity Siglec ligands that are useful for isolating cells that express Siglecs and for delivering agents to cells that express Siglecs. In one embodiment, the invention provides a method for treating cancer in a mammal that involves administering a Siglec ligand of the invention to the mammal, where the Siglec ligand is linked to a therapeutic agent.

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

Abstract: An apparatus for tracking processing of commands between command sources and sinks includes a command directory. The command directory receives a command from at least one command source, receives signals from command sinks, generates status information corresponding to the command based on the command and the received signals, and stores the status information. The status information indicates to which command sink the command is to be routed, whether the command sink has accepted the command, and whether the command sink has completed processing the command. The command directory includes a command buffer having a plurality of directory entries. The command buffer stores a command and associated status information in a directory entry. The command buffer also includes free buffer logic which monitors the status information in each directory entry. Based on this monitoring, the free buffer logic determines whether a directory entry has been disabled or whether command tracking errors exist.

Abstract: A method and apparatus for prioritizing and routing commands from a command source to a command sink. The command directory receives and stores a command from at least one command source. The data buffer stores the data associated with the command in the allocated portion of the data buffer. Based on status information also stored by the command directory with respect to each command, routing logic in the command directory, corresponding to each command sink, identifies which commands stored in the command buffer to route to the command sink, and routes the identified commands to the command sink. The routing logic also determines a priority of the identified commands and routes the identified commands in order of priority.

Abstract: A global wire management apparatus and method for a multiple port random access memory (RAM) is disclosed. The RAM includes an array of stacked dual memory cell structures each including a common row/column decoder disposed between an upper memory cell and lower memory cell. The upper memory cell is situated adjacent upper transfer gate circuitry, and the lower memory cell is situated adjacent lower transfer gate circuitry. The decoder circuit is oriented vertically in the middle of the dual memory cell structure so that the true and complement decoder outputs may be fed upwards and downwards to the upper and lower transfer gate circuits. Wiring of the upper and lower transfer gate circuits may be effected completely at the local interconnect layer. Each of the write ports of the common decoder includes a NAND gate, an inverter, and a transfer gate for each of the upper and lower memory cells for controlling the transfer of data to the upper and lower memory cells.

Abstract: An improved apparatus and method for facilitating multiple write port access to a programmable memory apparatus is disclosed. A memory array, such as a random access memory array, includes a plurality of memory cells. A number of write ports are coupled to the memory array, each of which provides write access to individual memory cells of the memory array. Each of the write ports includes a NAND gate, an inverter, and a transfer gate. The NAND gate includes first and second inputs respectively coupled to a write row select line and a write column select line, and an output coupled to the input of the inverter and a first control input of the transfer gate. The output of the inverter is coupled to a second control input of the transfer gate. The input of the transfer gate is coupled to a data line, and the output of the transfer gate is coupled to a memory cell of the memory array.

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

Abstract: A process for controlling the glycosylation of protein in a cell wherein the cell is genetically engineered to produce one or more enzymes which provide internal control of the cell's glycosylation mechanism. A Chinese hamster ovary (CHO) cell line is genetically engineered to produce a sialyltransferase. This supplemental sialyltransferase modifies the CHO glycosylation machinery to produce glycoproteins having carbohydrate structures which more closely resemble naturally occurring human glycoproteins.