Patents by Inventor James R. Griffith
James R. Griffith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120252169Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Neil T. Tracht, Darrel R. Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Patent number: 8217511Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.Type: GrantFiled: July 31, 2007Date of Patent: July 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Neil T. Tracht, Darrel R Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Patent number: 7795980Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.Type: GrantFiled: June 13, 2008Date of Patent: September 14, 2010Assignee: Freescale Semiconductor, Inc.Inventors: James R. Griffiths, David M. Gonzalez, Elie A. Maalouf
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Patent number: 7741194Abstract: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal.Type: GrantFiled: January 4, 2008Date of Patent: June 22, 2010Assignee: Freescale Semiconductor, Inc.Inventor: James R. Griffiths
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Patent number: 7701285Abstract: Systems and methods are described for improving the startup linearization of a power amplifier. A bias network is provided to generate a bias signal during amplifier startup, and the amplifier is configured to produce an output signal in response to the input signal and the bias signal. A variable impedance is provided to couple the input signal and the output signal in parallel with the amplifier. A controller is configured to apply a weighting function to the variable impedance over at least a startup phase of the amplifier system. By applying a non-linear or other weighting function to the variable impedance during startup, the gain of the amplifier can be controlled to thereby extend a time period over which the output power of the amplifier increases in a generally linear manner toward an operating level.Type: GrantFiled: March 19, 2008Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: James R. Griffiths, David M. Gonzalez
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Publication number: 20090309663Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James R. Griffiths, David M. Gonzalez, Elie A. Maalouf
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Publication number: 20090237156Abstract: Systems and methods are described for improving the startup linearization of a power amplifier. A bias network is provided to generate a bias signal during amplifier startup, and the amplifier is configured to produce an output signal in response to the input signal and the bias signal. A variable impedance is provided to couple the input signal and the output signal in parallel with the amplifier. A controller is configured to apply a weighting function to the variable impedance over at least a startup phase of the amplifier system. By applying a non-linear or other weighting function to the variable impedance during startup, the gain of the amplifier can be controlled to thereby extend a time period over which the output power of the amplifier increases in a generally linear manner toward an operating level.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James R. Griffiths, David M. Gonzalez
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Publication number: 20090176348Abstract: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: James R. Griffiths
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Publication number: 20090051435Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).Type: ApplicationFiled: August 20, 2007Publication date: February 26, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James R. Griffiths, David M. Gonzalez
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Patent number: 7489202Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).Type: GrantFiled: August 20, 2007Date of Patent: February 10, 2009Assignee: Freescale Semiconductor, Inc.Inventors: James R. Griffiths, David M. Gonzalez
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Publication number: 20090032933Abstract: Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventors: Neil T. Tracht, Darrel R. Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Publication number: 20080102762Abstract: A hybrid antenna switching system in a communications device generally includes an antenna, a first switching device, and a second switching device. The first switching device is configured to selectively couple the antenna to a first set of communication paths within the communications device, wherein the first set of communication paths includes at least one transmit path associated with a first type of wireless communication standard (e.g., a global system for communication (GSM) standard). The second switching device is configured to selectively couple the antenna to a second set of communication paths within the communications device, wherein the second set of communication paths includes at least one reception path associated with the first type of wireless communication standard. The second switching device is a micro-electromechanic system (MEMS) switch integrated with the first switching device on, for example, a common printed circuit board (PCB) or multi-chip module (MCM) substrate.Type: ApplicationFiled: October 30, 2006Publication date: May 1, 2008Inventors: Lianjun Liu, James R. Griffiths
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Patent number: 6317002Abstract: A multiple power low power radio frequency amplifier. A first transistor amplifies a radio frequency signal at a substantially peak efficiency. The amplified signal is fed to a first impedance matching network. A second transistor receives the radio frequency signal and amplifies the signal at peak efficiency. The second transistor amplifier is connected to a second impedance matching network. A control circuit selectively applies a signal to be amplified to each of the transistors. One or more of the transistors may be enabled to amplify the radio frequency at the transistors peak operating efficiency independent of whether the other of the transistors is enabled to amplify the signal.Type: GrantFiled: June 27, 2000Date of Patent: November 13, 2001Assignee: International Business Machines CorporationInventor: James R. Griffiths
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Patent number: 6297696Abstract: Apparatus and method for reducing reflected power in a radio frequency amplifier. A first directional coupler divides the radio frequency signal to first and second quadrature signals. First and second amplifiers amplify each of the quadrature signals. A second directional coupler combines signals from the amplifiers to produce a combined signal. A third directional coupler samples a portion of the reflected power received on the second directional coupler output. A control signal is derived from sampling the reflected power. A variable load impedance connected to the remaining output port of the second directional coupler has an impedance value which changes with respect to a control signal and the impedance is varied so as to substantially match the impedance received by the first output port.Type: GrantFiled: June 15, 2000Date of Patent: October 2, 2001Assignee: International Business Machines CorporationInventors: Mehdy Abdollahian, James R. Griffiths, Theodore L. Tewksbury
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Patent number: 5912286Abstract: A composition comprises a leachable organic compound distributed throughout a polymer matrix formed by reacting a fluoroepoxy compound of the formula: ##STR1## wherein x is an integer from 0 to 12, with a silicone amine curing agent of the formula: ##STR2## where n is the average degree of polymerization of the silicone amine curing agent and is 1 or greater. The leaching rate of the leachable organic compound is controlled by selecting the value of x in the fluoroepoxy compound and the value of n in the silicone amine curing agent. The composition may be used as a coating for protecting underwater substrates from fouling by marine organisms.Type: GrantFiled: August 29, 1997Date of Patent: June 15, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: James R. Griffith, Stephen L. Snyder
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Patent number: 5733606Abstract: A metallization is coated with a network polymer. The network polymer may either a cross-linked polyfluorinated polyallylether-polyhydromethylsiloxane copolymer or a network polymer formed from cross-linked fluoromethylene cyanate ester monomers. These polymer networks are resistant to the diffusion of a metallization, such as copper, therethrough.Type: GrantFiled: February 28, 1997Date of Patent: March 31, 1998Assignee: The United States of America as represented by the Secretary of the NavyInventors: Leonard J. Buckley, Arthur W. Snow, James R. Griffith, Mark Ray
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Patent number: 5708116Abstract: A reaction product of a liquid monomeric allyletherfluoroalkylene benzene d a liquid polymethylhydrosiloxane, which reaction product in a cured, solid state has dielectric constant below about 2.5.Type: GrantFiled: May 31, 1995Date of Patent: January 13, 1998Assignee: The United States of America as represented by the Secretary of the NavyInventors: James R. Griffith, Henry S. W. Hu
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Patent number: 5660920Abstract: A metallization is coated with a network polymer. The network polymer may be either a cross-linked polyfluorinated polyallylether-polyhydromethylsiloxane copolymer or a network polymer formed from cross-linked fluoromethylene cyanate ester monomers. These polymer networks are resistant to the diffusion of a metallization, such as copper, therethrough.Type: GrantFiled: July 14, 1995Date of Patent: August 26, 1997Assignee: The United States of America as represented by the Secretary of the NavyInventors: Leonard J. Buckley, Arthur W. Snow, James R. Griffith, Mark Ray
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Patent number: 5593732Abstract: A nontoxic antifouling system is provided at ambient conditions on a subste which has a solid release layer bonded to a solid bonding layer which in turn is bonded to said substrate. The release layer has excellent release property and is bonded to the bonding layer. The bonding layer contains a component which is believed to react with the same or a similar component in the release layer to enhance the desired bond therebetween. The bonding layer is tougher than the release layer but its release property is inferior to that of the release layer.Type: GrantFiled: April 28, 1995Date of Patent: January 14, 1997Assignee: The United States of America as represented by the Secretary of the NavyInventor: James R. Griffith
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Patent number: 5449553Abstract: A nontoxic antifouling system is provided at ambient conditions on a subste which has a solid release layer bonded to a solid bonding layer which in turn is bonded to said substrate. The release layer has excellent release property and is bonded to the bonding layer. The bonding layer contains a component which is believed to react with the same or a similar component in the release layer to enhance the desired bond therebetween. The bonding layer is tougher than the release layer but its release property is inferior to that of the release layer.Type: GrantFiled: March 28, 1994Date of Patent: September 12, 1995Assignee: The United States of America as represented by the Secretary of the NavyInventor: James R. Griffith