Abstract: A regulated power supply apparatus and method is provided. A converter circuit is configured to generate a regulated voltage signal from an unregulated voltage signal. A power sequencing circuit includes an unregulated voltage source input terminal and is configured for coupling an unregulated voltage signal to an unregulated voltage signal input terminal of the converter circuit. The power sequencing circuit includes an enable output coupled to the enable signal input terminal and includes a power limiting circuit and a trigger circuit. The power limiting circuit includes a first cascade of discrete analog components as controls for a first switching element and the trigger circuit includes a second cascade of discrete analog components as controls for a second switching element. The first cascade is configured as a charge control circuit for controlling a rate of charge of a first filter network and includes a zener diode coupled in parallel.

Abstract: An air inlet diffuser 10 is disclosed for attachment relative to an air inlet opening 106 of an electronics enclosure 100. The diffuser 10 extends into the electronics enclosure 100 and provides an increased surface area through which EMI attenuating apertures may be formed. The diffuser 10 also reduces the amount of structure that is disposed within the air inlet opening 106 thereby reducing impedance to airflow through the opening 106 into the enclosure 100. The increased surface are of the diffuser 10 allows for increasing the number of EMI attenuating apertures that may be utilized for a given inlet opening 106. In one embodiment, the total open area of the EMI apertures is greater than the open area of the air inlet opening. In such an embodiment, the EMI apertures provide low impedance to airflow through the diffuser 10 and increased airflow in conjunction with EMI attenuation may be realized.

Abstract: A method of interfacing for packet and cell transfer between a first layer device and a second layer device, which includes dividing control information into an in-band portion and an out-of-band portion, transmitting the in-band portion in the data path, and transmitting the out-of-band portion outside of the data path.

Abstract: An air inlet diffuser 10 is disclosed for attachment relative to an air inlet opening 106 of an electronics enclosure 100. The diffuser 10 extends into the electronics enclosure 100 and provides an increased surface area through which EMI attenuating apertures may be formed. The diffuser 10 also reduces the amount of structure that is disposed within the air inlet opening 106 thereby reducing impedance to airflow through the opening 106 into the enclosure 100. The increased surface are of the diffuser 10 allows for increasing the number of EMI attenuating apertures that may be utilized for a given inlet opening 106. In one embodiment, the total open area of the EMI apertures is greater than the open area of the air inlet opening. In such an embodiment, the EMI apertures provide low impedance to airflow through the diffuser 10 and increased airflow in conjunction with EMI attenuation may be realized.

Abstract: An air inlet diffuser 10 is disclosed for attachment relative to an air inlet opening 106 of an electronics enclosure 100. The diffuser 10 extends into the electronics enclosure 100 and provides an increased surface area through which EMI attenuating apertures may be formed. The diffuser 10 also reduces the amount of structure that is disposed within the air inlet opening 106 thereby reducing impedance to airflow through the opening 106 into the enclosure 100. The increased surface are of the diffuser 10 allows for increasing the number of EMI attenuating apertures that may be utilized for a given inlet opening 106. In one embodiment, the total open area of the EMI apertures is greater than the open area of the air inlet opening. In such an embodiment, the EMI apertures provide low impedance to airflow through the diffuser 10 and increased airflow in conjunction with EMI attenuation may be realized.

Abstract: A method of interfacing for packet and cell transfer between a first layer device and a second layer device, which includes dividing control information into an in-band portion and an out-of-band portion, transmitting the in-band portion in the data path, and transmitting the out-of-band portion outside of the data path.

Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as a repeater in a communication system. The PHY repeater supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. When the pass all symbols, pass violation symbols and pass line states modes are enabled, the PHY device operates as a "transparent" repeater. The repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The repeater also allows line states to be repeated without station management software. A single repeater may be used to couple two stations or multiple repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Abstract: An interface system for transferring information between a local area-network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system, An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Abstract: A physical layer controller for use in a data transmission network is disclosed which includes an automatic scrubbing arrangement that is activated upon the occurrence of a physical layer controller reconfiguration. The transmitter output port as well as each channel output of the physical layer controller has an output dirty flag associated therewith. Similarly, the input port as well as each channel input has an associated input dirty flag. A scrubbing arrangement automatically scrubs certain outputs after a configuration change. More specifically, in the absence of a blocking condition after a configuration change, the scrubbing arrangement will automatically scrub each output which has a new source and one of: 1) its associated output dirty flag is set to a first level; and 2) it is connected to an new source which has its associated input dirty flag set to a first level. In a method aspect, output dirty flags are set for each output that has the potential to transmits a data frame.

Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Abstract: In a communication network, an efficient link error monitor is provided that completely relieves the microprocessor of computing the link error rate and comparing it with link error rate thresholds. The link error rate computation and the comparison are performed by the physical layer of a communication station. The physical layer generates an interrupt to the microprocessor only if a threshold is crossed and a microprocessor action may be required. The physical layer includes a number of registers that can be conveniently written by the microprocessor to designate the thresholds and monitor the link errors. The link error rate is estimated using a simple estimator that provides a realistic link error rate estimate even at early stages of operation when few link errors have been detected and when, therefore, little statistical information on the link error rate exists.

Abstract: A network station's elasticity buffer includes a memory core together with write and read pointer logic. The memory core includes a START area and a CONTINUATION area which is a cyclic buffer. Under normal conditions, the read pointer follows the write pointer cyclically in the CONTINUATION area. However, upon detection of a start delimiter or upon station reset, the pointers recenter to the START area. Separate synchronizing logic is provided for each of the two recentering modes to reduce metastability problems caused by asynchronous sampling of data.

Abstract: A symbol-wide elasticity buffer for a receive/transmit station within an asynchronous data transmission network provides both for reframing after each packet and for the handling of a continuous line state symbol for a period longer than the allowed packet size. According to one aspect of the invention, the elasticity buffer is divided into a START section and a CONTINUATION section. The buffer's write pointer will not enter the CONTINUATION section until the read pointer is directed to the first of the multiple, sequential registers comprising the START section. The read pointer must sequentially read the START section registers before entering the CONTINUATION section. Once the write pointer or read pointer leaves the START section, it can only reenter the START section upon receipt of a start delimiter signal. When the write pointer or the read pointer reaches the last register in the CONTINUATION section, it is automatically routed back to the first CONTINUATION section register.

Abstract: A system, for counting the occurrence of a plurality of system events and for prioritizing the order in which count values are to be incremented, receives a plurality of data signals (15) where each signal is associated with a system event. The data signals (15) are stored in a storage register (16). A memory device (12) stores a plurality of count values, where one count value is associated with each system event to be counted. Each count value is stored in a preselected memory location. The storage register (16) also receives a feedback signal (32) to update the signals (15) stored in the register (16). The storage register (16) generates a plurality of signals (19) which are input to a priority decoder (14) and the priority decoder (14) generates a priority signal (32) to address the location in the memory device (12) where the count value to be accessed is stored.

Abstract: Apparatus and methods for encoding information characters received by a station from a transmission medium to generate internal code points for retrieval or retransmission by the station. The encoding provides an internal symbol set that is able to pass complete line state information via its internal code points, thereby eliminating the need for extra signals to indicate the current line state. The code points can also report error situations, such as elasticity buffer errors, and can be accepted by the station's transmitter to be encoded and, after appropriate filtering, repeated onto the transmission medium. The internal code points are optimized so that the code point set minimizes the decoding logic at the receiving end, be it the station's Media Access Control function or its transmitter. Furthermore, internally, the station may make use of the internal code points to synchronize the receiver elasticity buffer.

Abstract: A first-in, first-out (FIFO) memory configuration comprising a fully addressable memory (e.g. random access memory), a write pointer, a read pointer, and a third, "commit" pointer serving as a boundary between first and second subsets of data stored within the FIFO. During data reception, a comparator circuit compares a predetermined subset of imcoming data with a predefined reference data set for determining whether the incoming data should be stored or aborted. This determination establishes the appropriate memory address value for positioning the commit pointer. The first subset of data behind the commit pointer may selectively be stored, while the second subset of data ahead of the commit pointer may selectively be aborted. During data transmission, a status register monitors the readiness of the data medium onto which the data is to be transmitted. If and/or when the data medium is ready to accept data, the commit pointer may be selectively positioned to demarcate data committed for transmission.