Abstract: A method and apparatus for synchronizing the cascaded, multi-channel transmission of a plurality of data characters is provided. Each sequence of data characters preceded by a start delimiter. Each transmission channel provides transmitted data frames to an associated elasticity buffer. As each channel detects a start delimiter, it asserts a begin-request signal that acknowledges detection of the start delimiter. When all channels have detected a start delimiter, a read-start signal is asserted to simultaneously advance the read pointer of each elasticity buffer. In this manner, each elasticity buffer initiates a sunchronized read for local use or retransmission of the multi-channel data.

Abstract: A tightly coupled data processing system having high performance characteristics, including at least one general purpose host processor coupled to host processor ports of a High Performance Storage Unit, and a Scientific Processor directly coupled to scientific processor ports of the High Performance Storage Unit is described. The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. Provision is also made for the Scientific Processor to share the virtual address space of the host processor. A tightly coupled system is also disclosed wherein a plurality of general purpose host processors are each coupled to one or more High Performance Storage Units, and a Multiple Unit Adapter is utilized to couple an associated Scientific Processor to all of the High Performance Storage Units.

Abstract: An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry.

Abstract: A loop control mechanism is described for use in a vector-oriented scientific data processing system. Because of the vector-oriented nature of scientific programs used on digital data processing systems the efficient control of program loops is of major importance. It can be shown that a procedure coded as N nested DO loops in FORTRAN will generally require 2N-1 nested loops of scientific processor object code, given a vector register architecture. Except for the innermost level, it is necessary at each level to iterate by strips up to the vector length and within that vector length strip to iterate by elements. For the innermost loop, iteration by element is not needed, but is implicit in vector operations. The present mechanism accomplishes this loop control optimization by maintaining the parameters for loop control in separate loop control registers. The use of this special facility for these parameters provides for their efficient management.

Abstract: In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to segments to the bulk memory without replacement is accomplished in accordance with an age since first write algorithm.

Abstract: A local store for a scientific vector processor which provides high speed access to scalar variables, parameters, temporary operands, and register save area contents of the system. Basically, the local store is a general purpose storage structure which provides access which is as fast as access to the general or vector registers of the vector processor. It is capable of being accessed either directly or indirectly via indexing. It resides in the virtual address area of the machine so that it is accessible for either reading or writing by the host programs. Because of its positioning in relation to the high performance main storage unit its size is transparent to the other programs of the system since it overflows automatically into the main storage unit. It also has multiple interfaces which provide a more simple matching of the bank widths and transfer rates of the rest of the scientific processor.

Abstract: In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write. The host processor passes an AGEOLD parameter to the memory subsystem and this parameter regulates the trickling of segments. Unless the memory system is idle (no I/O activity), no trickling takes place until the age of the oldest written-to segment is at least as great as AGEOLD. A command is generated for each segment to be trickled and the priority of execution assigned to such commands is variable and determined by the relationship of AGEOLD to the oldest age since first write of any of the segments. If the subsystem receives no command from the host processor for a predetermined interval, AGEOLD is ignored and any written-to segment becomes a candidate for trickling.

Abstract: A run-length-limited group coding system is provided wherein the code permits a high data transfer efficiency. Code values for both data and control functions are chosen such that the maximum cumulative DC deviation from a nominal center is no more than 10 percent averaged over a data transmission sequence. The code employed limits the maximum number of zero bits between successive one bits in a serial binary sequence to a predetermined value thereby permitting self-clocking. The coding system is particularly suitable for use in baseband data transmission systems where the transmission medium is either an electrical or optical link. Code values for control functions meet the same constraints as those for data and protocols are established such that the coding system may be integrated into a variety of multiple-unit system configurations wherein the communication between units is, for example, by way of a point-to-point link, or a bus, star, loop, or ring arrangement.

Abstract: In a data processing system including a processor, a bulk memory, a cache, and a storage control unit for controlling the transfer of data between the bulk memory and the cache, a timestamp is generated with each write command. A linked list is maintained, having an entry therein corresponding to each segment in the cache which has been written to since it was moved from the bulk memory to the cache. The timestamp accompanying a write command which is the first command to write to a segment after that segment is moved from bulk memory to the cache is entered into the list at the most recently used position. An entry in the linked list is removed from the list when the segment corresponding thereto is transferred from the cache to the bulk memory. The linked list is utilized to update a value TOLDEST, which represents the age of the oldest written-to segment in the cache that has not been returned to bulk memory since it was first written to.