Abstract: An output driver circuit including first and second cascoded scaled P-channel devices coupled to first and second cascoded scaled N-channel devices. The P-channel devices are coupled together at a first node and between an output and a first source voltage having an elevated voltage level. The N-channel devices are coupled between the output and a reference source voltage. The first scaled P-channel device has a gate that receives a pull-up signal and the second scaled P-channel device has a gate coupled to a static voltage. The second P-channel device and the static voltage are configured to protect the first P-channel device from gate oxide breakdown when the first device is turned off. The first N-channel device has a gate receiving a voltage-limited pull-down signal and the second N-channel device has a gate receiving a lower voltage pull-down signal. The cascoded N-channel devices divide load and prevent hot carrier injection effects.

Abstract: An apparatus and method are provided for accelerating the evaluated output of an N-domino latch. The apparatus includes evaluation N-logic, latching logic, keeper logic, and acceleration logic. The evaluation N-logic is coupled to a first P-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an-evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node.

Abstract: An apparatus and method are provided that enable a computing device to make graceful power state transitions that do no impose unnecessary power surge compensations requirements on associated power sources. The apparatus has power control logic that is configured to determine if the computing device is to enter a low power state. The power control logic includes a plurality of stop signals. Each of the plurality of stop signals sequentially indicates that a corresponding clock signal be stopped, where the corresponding clock signal is operatively coupled to a corresponding sector logic element within the computing device.

Abstract: An input receiver with hysteresis including a differential sense amplifier, a reference circuit having a reference node providing a reference signal at a nominal threshold voltage level, and a switching stack device. The amplifier has a first input which receives an input signal, a second input coupled to the reference node, and an output which provides an output signal having first and second states indicative of the input signal. The switching stack device operates to adjust the reference signal based on the output signal between upper and lower threshold levels in an opposite direction of the input signal. The reference circuit may be a voltage divider that divides a power voltage signal to develop the reference signal. The switching stack device may include a P-channel device and an N-channel device coupled to the voltage divider to adjust the threshold voltage level of the reference signal.

Abstract: A timing debug tool for an IC that enables varying the skew of selected edges of a primary clock signal for a controllable number of clock cycles. The debug tool enables identification, isolation and analysis of timing problems on the IC. An IC including programmable clock skew logic that applies a programmed skew amount to selected edges of a clock signal. A debug system including clock control logic further including a delay block and test logic. The delay block delays a selected number of transitions of a first clock signal to provide a second clock signal, where each selected transition of the second clock signal is delayed, based on a sync signal, by either one of a default skew amount and a programmed skew amount. The test logic enables dynamic control of the sync signal and dynamic programming of the selected skew amount.

Abstract: An impedance controller that controls termination impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one termination logic element, and an impedance matching controller. The programmable reference impedance generator develops a reference impedance controlled by a reference impedance control input. Each termination logic element includes a programmable termination impedance generator coupled to a corresponding output and controlled by termination impedance control input. The impedance matching controller continually adjusts the reference impedance control input to match the reference impedance with the reference value within a predetermined tolerance and generates the termination impedance control input based on the reference impedance control input.

Abstract: A dynamic logic register including a dynamic circuit, a delayed inverter, a latching circuit, and a keeper circuit. The dynamic circuit pre-charges a pre-charged node while a clock signal is low and evaluates a logic function to control the state of the pre-charged node when the clock goes high. The delayed inverter provides an inverted and delayed clock. The latching circuit controls the state of an output node based on the pre-charged node during an evaluation period beginning when the clock goes high and ending when the inverted delayed clock next goes low. The latching circuit presents a tri-state condition to the output node and the keeper circuit maintains the state of the output node between evaluation periods. The register is very fast with zero setup and short data-to output-time, and may be used between stages in a pipeline system.

Abstract: An output impedance bias compensation system for adjusting output impedance of at least one output including a reference impedance generator, an impedance matching controller, at least one output impedance generator, and a programmable bias controller. The reference impedance generator develops a reference impedance based on a reference value. The impedance matching controller continually adjusts an input of the reference impedance generator to match the reference value within a predetermined tolerance. Each output impedance generator is coupled to a corresponding output and is controlled by an output impedance control input. The programmable bias controller combines a bias amount with the value of the input of the reference impedance generator to provide the output impedance control input. The bias controller is programmable to provide a bias amount to compensate for any process variations between the reference impedance generator and each output impedance generator.

Abstract: An output driver impedance controller for controlling pull-down impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one output driver coupled to a corresponding output, and an impedance matching controller. The programmable reference impedance generator develops a reference impedance controlled by a reference impedance control input. Each output driver includes a programmable output impedance generator coupled to an output and controlled by an output impedance control input. The impedance matching controller continually adjusts the reference impedance control input to match the reference impedance with the reference value within a predetermined tolerance and generates the output impedance control input based on the reference impedance control input. Each of the programmable generators may be implemented with a binary array of matched impedance devices.

Abstract: A digital level shifter for driving the input of a scaled P-channel driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted range biases the voltage associated with a logic signal from a lower voltage level to an intermediate level to preclude gate-oxide breakdown and protect the scaled driver device. The digital level shifter is implemented using digital devices thereby avoiding analog bias devices. The digital level shifter and the scaled driver device may be implemented on the same integrated circuit (IC) and fabricated using the same process as core circuitry so that the IC may directly interface external devices operating at elevated voltage levels without damaging the core circuitry or the scaled driver device.

Abstract: A microprocessor with multiple random bit generators is disclosed. The multiple random bit generators each generate a stream of random bits. One of the streams of random bits is selected to be used to accumulate into random bytes for provision to application programs. Which of the multiple random bit generator random bit streams is selected is determined by a selection value stored in a control register of the microprocessor. The selection value is programmable by an instruction executed by the microprocessor.

Abstract: A multiple mode clock receiver including first and second input AC-coupled capacitors, first and second voltage dividers and a differential amplifier. The voltage dividers each include first and second junctions, respectively, coupled to the first and second AC-coupled capacitors, respectively. The differential amplifier has first and second inputs coupled to the first and second junctions, respectively, and an output providing an output clock signal that is aligned with an input clock signal provided through the AC-coupled capacitors. The multiple mode clock receiver is a single circuit that aligns the output clock signal to any one of multiple forms of input clock signals, including a sole single-ended clock signal, a single-ended clock signal with a corresponding reference signal, and a differential clock signal.

Abstract: An IC including skew-programmable clock buffers, fixed skew logic, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed skew logic enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic is implemented as any type of permanent programmable block, such as laser-blown fuses, an EPROM, etc.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: An output driver circuit including first and second cascoded scaled P-channel devices coupled to first and second cascoded scaled N-channel devices. The P-channel devices are coupled together at a first node and between an output and a first source voltage having an elevated voltage level. The N-channel devices are coupled between the output and a reference source voltage. The first scaled P-channel device has a gate that receives a pull-up signal and the second scaled P-channel device has a gate coupled to a static voltage. The second P-channel device and the static voltage are configured to protect the first P-channel device from gate oxide breakdown when the first device is turned off. The first N-channel device has a gate receiving a voltage-limited pull-down signal and the second N-channel device has a gate receiving a lower voltage pull-down signal. The cascoded N-channel devices divide load and prevent hot carrier injection effects.

Abstract: A digital level shifter for driving the input of a scaled P-channel driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted range biases the voltage associated with a logic signal from a lower voltage level to an intermediate level to preclude gate-oxide breakdown and protect the scaled driver device. The digital level shifter is implemented using digital devices thereby avoiding analog bias devices. The digital level shifter and the scaled driver device may be implemented on the same integrated circuit (IC) and fabricated using the same process as core circuitry so that the IC may directly interface external devices operating at elevated voltage levels without damaging the core circuitry or the scaled driver device.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The random number generator includes a first variable frequency oscillator, a second variable frequency oscillator, and frequency variation logic. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency. Bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The frequency variation logic is coupled to the second variable frequency oscillator. The frequency variation logic generates a noise signal that directs the second variable frequency oscillator to vary the second frequency.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The apparatus has a first variable frequency oscillator, a second variable frequency oscillator, and a variable bias generator. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The a second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency, where bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The variable bias generator is coupled to the first and second variable frequency oscillators, and generates an analog bias signal. The first and second frequencies vary according to the analog bias signal, and the analog bias signal varies based upon logic states of a plurality of bits of the random number.

Abstract: A multi-level game board apparatus has a plurality of transparent, planar game boards each having a plurality of marker seats arranged in a pattern for receiving game markers, and a plurality of support shaft assemblies extending at spaced intervals through the peripheral edges of the game boards to secure the game boards together and hold them apart at a predetermined vertical spacing during game play. The apparatus is movable between an upright, deployed position in which each support shaft assembly is in a vertically extended position holding the game boards apart, and a collapsed, storage position in which each support shaft assembly is collapsed downwardly between each adjacent pair of boards to allow the boards to move closer together into a more compact, storage configuration. A locking device releasably secures the boards together in the collapsed, storage position.