Abstract: A CMOS slew-controlled split-voltage output driver is provided whose I/O logic is supplied at one (higher) voltage level and whose computational logic is supplied at a second (lower) voltage level. The slew-controlled split-voltage output driver includes an output driver circuit, a driver control circuit, and a feedback-enhanced level translator circuit. The output driver circuit drives the output signal to a low level, a high level, or a tri-state level. The driver control circuit receives an enable signal, and employs the enable signal to control turn on and turn off of the N-channel sink transistor. The feedback-enhanced level translator circuit receives an output state signal whose highlevel state is essentially equal to a second power supply voltage. The feedback-enhanced level translator circuit generates the enable signal to the level essentially equal to the first power supply voltage, and isolates generation of the enable signal from operation of the driver control circuit.

Abstract: A multi-level game board apparatus has a plurality of transparent, planar game boards each having a plurality of marker seats arranged in a pattern for receiving game markers, and a plurality of support shaft assemblies extending at spaced intervals through the peripheral edges of the game boards to secure the game boards together and hold them apart at a predetermined vertical spacing during game play. The apparatus is movable between an upright, deployed position in which each support shaft assembly is in a vertically extended position holding the game boards apart, and a collapsed, storage position in which each support shaft assembly is collapsed downwardly between each adjacent pair of boards to allow the boards to move closer together into a more compact, storage configuration. A locking device releasably secures the boards together in the collapsed, storage position.

Abstract: A digital phase lock loop synchronizes a first signal to a second signal having a predefined frequency. The first signal usually has an instantaneous frequency greater than the predefined frequency, so that the first signal is constantly gaining phase with respect to the second signal. The digital phase lock loop performs periodic correction cycles by detecting a predefined phase relationship between the first signal and the second signal, and when the predefined phase relationship is detected, expanding the first signal in phase by a predetermined amount. Preferably, the first signal is generated by clocking a frequency divider with a clocking frequency, and the first signal is expanded in phase by inhibiting the clocking of the frequency divider for one clocking cycle for each correction cycle. Preferably, the predetermined phase relationship is detected when the second signal has a predetermined logic state coincident with clocking by the clocking signal and a predetermined state of the frequency divider.

Abstract: A data processing system has operational management registers containing attributes that are used during an application to optimize operation of the data processing system for energy, time, or costs based on the type of operation being performed by the data processing system. The data processing system can implement a different operation management technique dynamically while the program is active within the data processing system.

Abstract: An apparatus and method for measuring parasitic differences between dissimilar conductive paths on a semiconductor is provided. The apparatus provides a ring oscillator which has two propagation paths. The first path is traversed on a logical transition from low to high, and the second path is traversed on a logical transition from high to low. The gate stages for the first path may be interconnected via a metal conductive layer, and the gate stages for the second path may be connected to a dissimilar metal, or polycide, for example. A single output signal is produced which has a period equal to twice the delay of the inverter stages, plus any delay associated with the parasitic difference in the two paths. The duty cycle of the periodic signal may then be used to determine the parasitic difference between the two materials used to interconnect the stages in the ring oscillator.

Abstract: An apparatus and method which provides specified hold times for communication signals transmitted from a processing device that is capable of operating at different frequencies, to external devices, is provided. The apparatus includes a clock multiplier which generates an internal clock signal which is a multiple of an external clock, a ring oscillator, which provides a number of outputs of the same frequency as the internal clock, but at fixed phase offsets from the internal clock, and clock select circuitry, which selects one of the outputs from the ring oscillator, depending on the speed of the internal clock, to be used as a drive clock signal for a bus unit. Selection of one of the phase offset outputs provides for a specified hold time regardless of the internal clock speed of the processing device.

Abstract: A method and apparatus for reducing power associated with acquiring phase-lock between a reference clock signal and an internal clock signal after each exit from a quiescent state by a data processing system. A phase-locked loop (PLL) phase-locks the internal clock signal to the reference clock signal. A set of clock drivers receive an oscillator signal from the PLL and generate a plurality of multi-phase internal clock signals in response thereto. The clock state machine receives a first control signal from the PLL, indicating that the phase-locked loop is re-acquiring phase-lock as a result of the data processing system leaving a quiescent state. The clock state machine suppresses a set of clock state signals to prevent the clock drivers from changing state during the period of time when the phase-locked loop is re-acquiring phase-lock.

Abstract: An integrated circuit (10), which is designed using standard cells (20, 22, 24, 26, 28, 30, 32, 34, 35, 36, 37, 28, 40, 42, 44, 46, 48, 50, 52), usually has one or more empty spaces (54) wherein no circuitry is formed. These empty spaces may be used to form capacitor standard cells which have capacitors (see FIGS. 3 and 4) to both ground and power supply lines within the integrated circuit. These capacitors are used to reduce noise in the power and supply lines in a manner more useful/efficient than known methods. The capacitor standard cell taught herein is more useful/efficient due to the fact that the capacitance provided by these standard cells is distributed over the entire integrated circuit in small portions (i.e., standard cells are placed all over the integrated circuit (10)), and is placed close to the logic which is switching. It is the switching logic which is the root of a large portion of internal integrated circuit noise.

Abstract: A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD, is of a voltage level greater than the minimum voltage level suitable for safely resolving CMOS logic. The power sense signal, when asserted, enables a small, on-chip ring oscillator. An output signal generated by the ring oscillator supplies a clocking signal to the clock drivers and to the clock state machine of the CPU, thereby providing internal clocks to a central processing unit (CPU). A counter counts the number of clock pulses provided to the CPU and disables the ring oscillator and the clock state machine (thereby stopping the internal data-processor clock drivers) when the accumulated number of clock pulses equals or exceeds a predefined number. The predefined number of internal clock pulses is the minimum number of clocks to process a reset condition that resolves all on-chip, CPU state conflicts and contention.

Abstract: A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.

Abstract: A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Abstract: A method and apparatus for performing, after frequency acquisition, phase acquisition and phase maintenance in a digital phase-locked loop 10. A phase detector (12), determines the phase relation of an oscillator output to a reference clock signal, and provides a control signal to a controller (13), indicative thereof. When a subsequent logic state of the control signal provided by the phase detector is equal to an initial logic state of the control signal, the controller (13) increments or decrements a control value initially corresponding to a baseline frequency of the oscillator by the gain value, based upon the logic state of the control signal. When the control signal changes state, phase-lock has been acquired, and a gain value which determines the magnitude of change of the oscillator frequency is decreased. On every subsequent change in the logic state of the control signal, the gain value is decreased, unless at a minimum.

Abstract: A method and apparatus for implementing a constant gain in a digitally-controlled variable oscillator (DCO) 16 where the frequency of the DCO 16 is controlled via binary-weighted control signals. The frequency of the DCO 16 is modulated via arithmetic increments or decrements to the binary-weighted DCO control signals. The magnitude of the arithmetic increments and decrements defines the gain of the DCO. To maintain a constant gain, regardless of operating point or environment, a phase gain register 15 bit-shifts a current DCO control value by a predefined number of bit positions, thereby determining a phase gain value. The phase gain value defines the magnitude of an arithmetic increment or decrement of the current DCO control value, used to determine the next DCO control value. Since the phase gain register 15 uses a bit-shifted version of the current value of the DCO control, the gain value dynamically tracks all updates to the DCO control value, thereby implementing a constant gain in the DCO 16.

Abstract: An output driver circuit has a circuitry portion (70) which is used to generate a Drive-Hi control signal in response to an Output Enable, an optional Precondition signal, and a Data Input signal. A circuit portion (75) ensures that the Drive-Hi control signal is maintained at a voltage which is substantially equal to Vdd when the Output Enable is deactivated. Circuit portion (80) selectively controls the Data Output by driving Vdd onto the Data Output in response to the Drive-Hi control signal being activated. A circuit portion (100) functions to selectively drive the Data Output to a logic zero (ground potential) when a Drive-Lo signal is asserted. Circuit portions (90 and 95) generate the Drive-Lo signal in response to the Output Enable, the optional Precondition signal, and the Data Input signal.

Abstract: An all digital phase lock loop (ADPLL), (10) includes a variable digital oscillator (DCO 16), a phase detector (12), a controller (13) including an incrementor (19) and decrementor (21), and a set of oscillator control registers (22). A frequency tracking circuit (20) is separated from the phase acquisition/maintenance logic circuitry. The frequency tracking circuitry (20) uses an anchor value to maintain and update a DCO control value corresponding to a target frequency of operation of the DCO (16). Updates to the anchor value are facilitated by monitoring recent history of an output control signal (ahead or behind) provided by the phase detector (12). The anchor value is changed to maintain the target frequency of operation of the DCO (16), even in the presence of variations in operating environments.

Abstract: A driver circuit employs an N-channel pull-down transistor of relatively small size, directly connecting an output node to ground, and another path consisting of a pair of series-connected N-channel transistors connecting the node to ground; the lower of these is driven by the logic voltage which is applied to the gate of the pull-down, and the other has its gate connected to the output node. Two parallel discharge paths are thus provided for the output node, one through the small pull-down transistor, and a second through the (larger) series transistors. When a returning wave from the output node (due to transmission line effects) hits the driver circuit, the series transistors turn off, but the pull-down transistor is still on keeping the driver output node at a valid "low." In cases of mismatch or noise, the pull-down transistor will help absorb refections or ringing.

Abstract: A tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with another N-channel transistor connected between the pull-up and pull-down transistors and having its gate connected to the low-voltage supply. An output node at one side of the pull-up transistor may be driven to a voltage higher than the supply, without subjecting the pull-up to hot-carrier effects or other deleterious effects of over-voltage. When in the high-impedance output state, the gate of the pull-up is shorted to an intermediate node which is the drain of the pull-down transistor, using a P-channel and an N-channel transistor responsive to the logic input. The voltage on the gate of the pull-up transistor is allowed to track the output up to the reduced voltage supply minus V.sub.TN when in the high-impedance state, by tying the gate of the pull-up transistor to the intermediate node; this prevents damage to the pull-up due to hot-carrier effects.

Abstract: A CMOS push-pull output buffer is powered by a low-voltage (e.g., +3.3 V) supply, but is able to withstand elevation of its output node to higher voltage without sinking large currents into the low-voltage supply. Thus, this buffer is able to operate tied to a bus that has various higher-voltage sources also operating on the bus. The P-channel pull-up transistor of this buffer has another P-channel transistor connecting its gate to the output node so that this gate will follow the voltage of the output node and thus keep the pull-up transistor from conducting from the output node to the power supply. The inverter which drives this gate of the P-channel pull-up transistor is also protected from reverse current into its low-voltage power supply by a series N-channel transistor which will exhibit body effect and is sized to present a significant resistance.