Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

Abstract: In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. The arbiter is coupled to the command queue to select memory access commands from the command queue according to predetermined criteria. In the virtual controller mode, the arbiter selects from among the memory access requests in each sub-channel independently using the predetermined criteria, and sends selected memory access requests to a corresponding one of a plurality of sub-channels. In another form, a data processing system includes a plurality of memory channels and such a memory controller coupled to the plurality of sub-channels.

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.

Abstract: In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. The arbiter is coupled to the command queue to select memory access commands from the command queue according to predetermined criteria. In the virtual controller mode, the arbiter selects from among the memory access requests in each sub-channel independently using the predetermined criteria, and sends selected memory access requests to a corresponding one of a plurality of sub-channels. In another form, a data processing system includes a plurality of memory channels and such a memory controller coupled to the plurality of sub-channels.

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A method is provided for issuing subcommands to a memory module using unassigned bits in a memory control protocol. A buffer component within the memory module receives the subcommands and modifies a state of the memory module accordingly. This allows, for example, selectively powering down individual ranks of the memory module (e.g., an LRDIMM memory module). Unassigned bits in a JEDEC-compliant ZQ calibration command set may be used for implementing such subcommands.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A circuit and method for correcting erroneous data in memory for pipelined reads. A memory controller includes a control unit, a storage unit and an error detection and correction unit. The control unit is configured to read data including an associated error correction code from a memory subsystem in response to a memory read request. The error detection and correction unit is coupled to receive the data and configured to determine whether an error exists in that data based upon the associated error correction code. The control unit is configured to store an indication in the storage unit that the data corresponding to the memory read request is erroneous. The control unit is further configured to detect the indication in the storage unit and to responsively perform a subsequent read of the data from the memory subsystem and to write a corrected version of the data back to the memory subsystem.

Abstract: A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.

Abstract: A processor-based system such as a workstation or server, using a system clock provided through a phase-locked loop (PLL) to a clock gate and then to a clock tree, which distributes the core system clock to components in the processor-based system, including a host bridge circuit. The host bridge distributes control signals to a receiving device such as a memory module, which may use a continued clocking signal when the system enters a low-power mode. A feedback clock for the PLL is provided to the receiving devices during low-power mode to ensure continued clocking, when the clock gate output is low and the clock tree is thereby disabled. A skew compensation circuit coordinates clocking in the continued clock and the core system clock.

Abstract: A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

Abstract: Improved performance for data read operation is achieved in a read buffer that receives and stores requested information in response to read requests from multiple requesting master devices. A full cache line of data is read from the memory device into the read buffer in response to any read request. The requested data and any additional data within the retrieved cache line is available to any requesting master device in zero wait states. In addition, a next cache line of data is retrieved concurrently while the previously stored data is provided to the requesting master pursuant to the original read request. Subsequent read requests that matches any data stored in the read buffer is provided pursuant to a subsequent read request in zero wait states.

Abstract: An arbitration mechanism for an input/output node of a computer system. An arbitration mechanism includes a buffer circuit for storing received control commands corresponding to a posted virtual channel and a second virtual channel. Each of the control commands includes an identifier value indicative of the source of the control command. A tag circuit that may generate a tag value for each of the control commands prior to the control commands being stored. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, an arbitration circuit may arbitrate between control commands stored within the buffer circuit dependent upon the tag value of each of the control commands. The arbitration circuit may select, independently of the tag values, a given control command and having a flag bit set.

Abstract: A system that enables a memory controller to control data transfers with memory modules, such as DIMMs (double in-line memory modules), of either a “by 4” (×4) type or a non-by-4 type (non-×4). Both ×4 and non-×4 DIMMs may be used in the system simultaneously, and the memory controller dynamically adjusts its enable and other signals as needed. Data strobe signals are provided to and from DIMMs over a data strobe transfer circuits which in the case of a non-×4 DIMM handles data strobes for an entire byte of data, while in the case of ×4 DIMM the data transfer circuit handles data strobes for one nibble (four bits) of a byte of data. A hybrid data mask/data strobe transfer circuit handles the other nibble of a byte of data in the case of data transfers for ×4 DIMMs, and handles data mask signals for write operations for non-×4 DIMMs.