Abstract: A write buffer includes master trace bits to enable a system debugger to determine the source of accesses to memory in systems with multiple masters. When a write to memory is initiated by one of a plurality of masters, the write buffer receives a grant signal, indicating which master is initiating the write operation, and stores the information as master trace bits. Likewise, when a read from memory is initiated by a master, the write buffer master trace bits reflect the requesting master. Accordingly, each rank in the write buffer may include master trace information. The master trace bits are particularly useful in write buffers which employ either write merging or write collapsing features. The master trace bits are further made available to system debuggers on pins external to the system or via a port accessible to software.

Abstract: An integrated circuit, system and method monitors parameter performance for optimization of controller performance. The integrated circuit includes a memory controller, one or more buffers coupled to the memory controller, and a performance monitoring circuit coupled to the one or more buffers and an SDRAM controller, the performance monitoring circuit to receive at least one parameter related to the buffers and provide statistical data related to the parameter. The statistical data may be used to set an amount of data to accumulate in the one or more buffers. A method includes transmitting one or more parameters related to performance of one more components of an integrated circuit to a performance monitoring circuit located within the integrated circuit. The performance monitoring circuit then determines statistical data related to the parameter independent of an interrupt to the integrated circuit.

Abstract: A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

Abstract: An invalid configuration detection resource for identifying and reporting conflicts between system resources of a microcontroller or other device is provided. Selected system registers within each resource are monitored by discrete hardware logic within the invalid configuration detection resource. For each resource, a status register provides an encoding of the configuration for that resource. The invalid configuration detection resource then compares the status registers for invalid combinations, and encodes this information in a system status register. Alternatively, the invalid configuration detection resource monitors each selected system register, independent of the resource to which it belongs. Improper combinations of registers are then encoded in a system status register. An alternative embodiment uses software to replace the discrete hardware logic with a table that specifies invalid register combinations.

Abstract: A processor-based system provides communication among multiple computer devices operating at different frequencies utilizing clock synchronization. Phase relationship is maintained between clock signals running a different frequencies such that a read cycle of a device operated at the faster frequency is initiated when the clock signals are in phase. A write cycle of the faster frequency device is initiated when the clock signals are out of phase. A synchronization signal is generated by sampling the clock signals together to indicate the phase relationship. In addition, a return clock, derived from the faster clock, drives external devices. Information sent from internal devices to external devices are passed through a register driven by the return clock. Timing delays for information presented to the external devices is avoided as the register transmits all information according to the return clock. Return data is clocked into a return register also according to the return clock.

Abstract: Briefly, a processor-based device, such as a microcontroller, provides a data bus that is shared by both non-volatile memory and volatile memory. The processor-based device also provides specialized signals to facilitate the data bus sharing. A non-volatile memory controller of the processor-based device provides a non-volatile memory busy signal and a non-volatile memory request signal to a volatile memory controller of the processor-based device. The non-volatile memory busy signal indicates to the volatile memory controller when the non-volatile memory controller controls the data bus. The non-volatile memory request signal indicates to the volatile memory controller when the non-volatile memory controller needs to use the data bus. The volatile memory controller provides a volatile memory busy signal to the non-volatile memory controller which informs the non-volatile memory controller when the data bus is controlled by the volatile memory controller.

Abstract: A communication protocol is implemented by a control bus using multi-purpose bi-directional signal lines. The bi-directional signal lines provide a single control path shared among any number of system devices. Tokens, defined by the combination of states of the bi-directional signal lines, are transmitted over the control bus to other system devices. A token can represent a number of control commands. A received token is decoded by a system device using decode logic into an appropriate control command associated with the token according to a predefined logic table. Since a token can represent a control command only originated target devices or a control command only originated by initiator devices, the control bus can support both types of control commands with fewer pincount and point-to-point connections than conventional unidirectional control signalling.

Abstract: A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller.

Abstract: A microcontroller for PC/AT-compatible or non-PC/AT compatible embedded environments is disclosed. The microcontroller includes a general purpose bus which may emulate an ISA bus in a PC/AT-compatible mode. PC/AT-compatible DMA channels, interrupt controllers, programmable timers, a real-time clock, processor, and a flexible memory and an I/O mapping scheme are provided by the microcontroller. The programmable timers, interrupt controllers, DMA channels and I/O mapping can be configured for a PC/AT-compatible mode or a non-PC/AT-compatible mode. In particular, the plurality of interrupt controllers are configured such that some are enabled during PC/AT-compatible operation while the remainder are disabled. The microcontroller further embeds several PC/AT peripheral devices and yet maintains the flexibility to support external devices if desired by the embedded system designer. Other PC/AT-compatible features are also supported by the microcontroller.

Abstract: A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters.

Abstract: A system provides a write buffer with random access snooping capability. A random access write buffer includes a write buffer controller and a random access memory (RAM) containing a content addressable memory (CAM) address store and a random access memory data store. The CAM compares an input write address from a producer to the addresses present in the address store. If the input write address is "related" to an address present in the address store, the CAM detects an address hit. The indication of an address hit is provided to the write buffer controller which signals the data store to store the input write data in the existing rank of the data store associated with the "related" address detected by the CAM. The CAM also detects whether an input read address provided by a producer to a consumer is "related" to an address in the address store.