Abstract: A pump panel training device is provided and includes a plurality of simulated gages operable to imitate gages upon a fire truck pump panel, a plurality of simulated controls operable to imitate controls upon the fire truck pump panel, and a simulated water hose operable to imitate one of water temperature changes, water temperature pressure, and water hose vibration for the fire truck pump panel.

Abstract: In one embodiment, a hermetic covering system includes a projectile and at least one bag. The projectile has a body and a component that houses moisture-sensitive equipment. The at least one bag may be coupled to the body such that the projectile protrudes through the opening and the component is disposed in the inner cavity to protect the component during storage of the projectile.

Abstract: An electronically scanned array antenna. The novel antenna includes a first planar array of antenna elements and one or more side planar arrays of antenna elements, each side array adjacent to the first array and tilted at a predetermined angle relative to the first array. In an illustrative embodiment, the antenna also includes a plurality of transmit/receive modules, each module coupled to one antenna element. Each transmit/receive module includes phase shifters for varying the relative phases of the antenna elements to form a desired overall beam pattern, and a low noise amplifier and high power amplifier for amplifying signals received and transmitted by the antenna element, respectively. In an illustrative embodiment, a processor provides individual phase and channel enable control signals for independently controlling the phase shifters and amplifiers, respectively, of each module.

Abstract: An apparatus and method for providing standby power to a node of a distributed system of devices. The apparatus includes: a current manager operable to manage supply of current to a device at the node; a normal current supplier operable to supply normal operating current to the device; and a super capacitor at the node operable to supply standby operating current to the device under control of the current manager when the normal current supplier fails to supply the normal operating current to the device. The apparatus preferably further comprises a switching regulator, operable in electrical communication with the super capacitor and the device, to regulate the standby operating current to the device.

Abstract: A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

Abstract: A partitioned aperture array antenna. The novel antenna includes a first subarray having a first number of antenna elements equipped with transmit functionality and a second subarray having a second number of antenna elements equipped with receive functionality, wherein the first and second numbers are not equal and the first and second subarrays have at least one common antenna element. In an illustrative embodiment, the first subarray includes a transmit circuit coupled to each antenna element in the first subarray for controlling a relative transmit phase of the antenna element to steer an overall antenna transmit beam, and the second subarray includes a receive circuit coupled to each antenna element in the second subarray for controlling a relative receive phase of the antenna element to steer an overall antenna receive beam.

Abstract: According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.

Abstract: A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

Abstract: A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

Abstract: In certain embodiments, a structure for electronic components includes a baseplate having a substantially planar shape. The baseplate defines one or more openings allowing air flow. The structure includes a frame coupled to the baseplate. The frame includes a planar support with a substantially planar shape that is substantially parallel to the baseplate. Then planar support and baseplate at least partially defines one or more plenums. The planar support is also configured to support one or more transmit/receive integrated microwave modules. The frame also includes a plurality of frame supports that define one or more channels for air flow. Each channel corresponds to one of the plenums. Additionally, the frame includes a ventilated panel with a surface defining a plurality of air inlets. The air inlets allow air into one of the one or more plenums. Also, the frame includes one or more thermal interfaces configured to dissipate heat.

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.

Abstract: A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

Abstract: Adjusting a calibrated phased array includes receiving conditions data describing conditions at a phased array. The phased array comprises antenna element sets, where an antenna element set comprises antenna elements and is associated with a calibration value. The following is performed for each antenna element set. A temperature value is established for an antenna element set according to the conditions data. A temperature-dependent correction value corresponding to the temperature value is established. A correction value is determined for the antenna element set according to the temperature-dependent correction value and the calibration value associated with the each antenna element set. At least one antenna element of the antenna element set is adjusted according to the correction value.

Abstract: In certain embodiments, a structure for electronic components includes a baseplate having a substantially planar shape. The baseplate defines one or more openings allowing air flow. The structure includes a frame coupled to the baseplate. The frame includes a planar support with a substantially planar shape that is substantially parallel to the baseplate. Then planar support and baseplate at least partially defines one or more plenums. The planar support is also configured to support one or more transmit/receive integrated microwave modules. The frame also includes a plurality of frame supports that define one or more channels for air flow. Each channel corresponds to one of the plenums. Additionally, the frame includes a ventilated panel with a surface defining a plurality of air inlets. The air inlets allow air into one of the one or more plenums. Also, the frame includes one or more thermal interfaces configured to dissipate heat.

Abstract: A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.

Abstract: An electronically scanned array antenna. The novel antenna includes a first planar array of antenna elements and one or more side planar arrays of antenna elements, each side array adjacent to the first array and tilted at a predetermined angle relative to the first array. In an illustrative embodiment, the antenna also includes a plurality of transmit/receive modules, each module coupled to one antenna element. Each transmit/receive module includes phase shifters for varying the relative phases of the antenna elements to form a desired overall beam pattern, and a low noise amplifier and high power amplifier for amplifying signals received and transmitted by the antenna element, respectively. In an illustrative embodiment, a processor provides individual phase and channel enable control signals for independently controlling the phase shifters and amplifiers, respectively, of each module.

Abstract: A partitioned aperture array antenna. The novel antenna includes a first subarray having a first number of antenna elements equipped with transmit functionality and a second subarray having a second number of antenna elements equipped with receive functionality, wherein the first and second numbers are not equal and the first and second subarrays have at least one common antenna element. In an illustrative embodiment, the first subarray includes a transmit circuit coupled to each antenna element in the first subarray for controlling a relative transmit phase of the antenna element to steer an overall antenna transmit beam, and the second subarray includes a receive circuit coupled to each antenna element in the second subarray for controlling a relative receive phase of the antenna element to steer an overall antenna receive beam.

Abstract: Adjusting a calibrated phased array includes receiving conditions data describing conditions at a phased array. The phased array comprises antenna element sets, where an antenna element set comprises antenna elements and is associated with a calibration value. The following is performed for each antenna element set. A temperature value is established for an antenna element set according to the conditions data. A temperature-dependent correction value corresponding to the temperature value is established. A correction value is determined for the antenna element set according to the temperature-dependent correction value and the calibration value associated with the each antenna element set. At least one antenna element of the antenna element set is adjusted according to the correction value.

Abstract: Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal.