Patents by Inventor James S. Papanu

James S. Papanu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079273
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 7, 2024
    Inventors: Jungrae Park, ZAVIER ZAI YEONG TAN, KARTHIK BALAKRISHNAN, JAMES S. PAPANU, WEI-SHENG LEI
  • Patent number: 11901232
    Abstract: Embodiments of the present disclosure include methods of determining scribing offsets in a hybrid laser scribing and plasma dicing process. In an embodiment, the method comprises forming a mask above a semiconductor wafer. In an embodiment, the semiconductor wafer comprises a plurality of dies separated from each other by streets. In an embodiment, the method further comprises patterning the mask and the semiconductor wafer with a laser scribing process. In an embodiment, the patterning provides openings in the streets. In an embodiment, the method further comprises removing the mask, and measuring scribing offsets of the openings relative to the streets.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Karthik Balakrishnan, Jungrae Park, Zavier Zai Yeong Tan, Sai Abhinand, James S. Papanu
  • Patent number: 11854888
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 26, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, Karthik Balakrishnan, James S. Papanu, Wei-Sheng Lei
  • Patent number: 11764061
    Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: September 19, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Wenguang Li, James S. Papanu
  • Publication number: 20230187215
    Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Sai Abhinand, Michael Sorensen, Karthik Elumalai, Dimantha Rajapaksa, Cheng Sun, James S. Papanu, Gaurav Mehta, Eng Sheng Peh, Sri Thirunavukarasu, Onkara Korasiddaramaiah
  • Publication number: 20230100863
    Abstract: Methods and apparatus for processing a substrate area provided herein. For example, methods for enhancing surface hydrophilicity on a substrate comprise a) supplying, using a remote plasma source, water vapor plasma to a processing volume of a plasma processing chamber to treat a bonding surface of the substrate, b) supplying at least one of microwave power or RF power at a frequency from about 1 kHz to 10 GHz and a power from about 1 kW to 10 kW to the plasma processing chamber to maintain the water vapor plasma within the processing volume during operation, and c) continuing a) and b) until the bonding surface of the substrate has a hydrophilic contact angle of less than 10°.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Prayudi LIANTO, Yin Wei LIM, James S. PAPANU, Guan Huei SEE, Eric J. BERGMAN, Nur Yasmeen Addina MOHAMED HELMI ISIK, Wei Ying Doreen YONG, Vicknesh SAHMUGANATHAN, Yi Kun Kelvin GOH, John Leonard SUDIJONO, Arvind SUNDARRAJAN
  • Patent number: 11600492
    Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sai Abhinand, Michael Sorensen, Karthik Elumalai, Dimantha Rajapaksa, Cheng Sun, James S. Papanu, Gaurav Mehta, Eng Sheng Peh, Sri Thirunavukarasu, Onkara Korasiddaramaiah
  • Publication number: 20220181142
    Abstract: Methods and apparatus for far edge trimming are provided herein. For example, an apparatus includes an integrated tool for processing a silicon substrate, comprising a vacuum substrate transfer chamber, an edge trimming apparatus coupled to the vacuum substrate transfer chamber and comprising a high pulse frequency laser and substrate support, wherein at least one of the high pulse frequency laser or the substrate support are movable with respect to each other and configured to trim about 2 mm to about 5 mm from a peripheral edge of a substrate when disposed on the substrate support, and a plasma etching apparatus coupled to the vacuum substrate transfer chamber and configured to etch silicon.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Inventors: Chien-Kang HSIUNG, James S. PAPANU, Arvind SUNDARRAJAN
  • Publication number: 20220076944
    Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: Wenguang Li, James S. Papanu
  • Patent number: 11217536
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 4, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Patent number: 11211247
    Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Wenguang Li, James S. Papanu
  • Publication number: 20210398854
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, Karthik Balakrishnan, James S. Papanu, Wei-Sheng Lei
  • Publication number: 20210398853
    Abstract: Embodiments of the present disclosure include methods of determining scribing offsets in a hybrid laser scribing and plasma dicing process. In an embodiment, the method comprises forming a mask above a semiconductor wafer. In an embodiment, the semiconductor wafer comprises a plurality of dies separated from each other by streets. In an embodiment, the method further comprises patterning the mask and the semiconductor wafer with a laser scribing process. In an embodiment, the patterning provides openings in the streets. In an embodiment, the method further comprises removing the mask, and measuring scribing offsets of the openings relative to the streets.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Inventors: Karthik Balakrishnan, Jungrae Park, Zavier Zai Yeong Tan, Sai Abhinand, James S. Papanu
  • Patent number: 11158540
    Abstract: Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Wenguang Li, James S. Papanu, Wei-Sheng Lei, Prabhat Kumar, Brad Eaton, Ajay Kumar, Alexander N. Lerner
  • Publication number: 20210242014
    Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 5, 2021
    Inventors: Wenguang Li, James S. Papanu
  • Publication number: 20210233816
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a spatially multi-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, James S. Papanu
  • Publication number: 20210175086
    Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Inventors: Sai Abhinand, Michael Sorensen, Karthik Elumalai, Dimantha Rajapaksa, Cheng Sun, James S. Papanu, Gaurav Mehta, Eng Sheng Peh, Sri Thirunavukarasu, Onkara Korasiddaramaiah
  • Patent number: 11011424
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a spatially multi-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: May 18, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, James S. Papanu
  • Publication number: 20210050263
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Inventors: Jungrae Park, Karthik Balakrishnan, James S. Papanu
  • Publication number: 20210043515
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a spatially multi-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, James S. Papanu