Patents by Inventor James S. Vickers
James S. Vickers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11353479Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.Type: GrantFiled: January 15, 2019Date of Patent: June 7, 2022Assignee: FEI EFA, Inc.Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
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Publication number: 20200025799Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.Type: ApplicationFiled: January 15, 2019Publication date: January 23, 2020Applicant: FEI EFA, Inc.Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
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Patent number: 10209274Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.Type: GrantFiled: October 23, 2015Date of Patent: February 19, 2019Assignee: FEI EFA, Inc.Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
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Patent number: 10126360Abstract: An apparatus and method for laser voltage testing of a DUT is disclosed. The system enables laser voltage probing and laser voltage imaging of devices within the DUT. A selected area of the DUT is illuminating a while the DUT is receiving test signals causing certain of the active devices to modulate. Light reflected from the DUT is collected and is converted into an electrical signal. The electrical signal is sampled by an ADC and the output of the ADC is sent to an FPGA. The FPGA operates on the signal so as to provide an output that emulates a spectrum analyzer or a vector analyzer.Type: GrantFiled: October 16, 2015Date of Patent: November 13, 2018Assignee: FEI EFA, Inc.Inventor: James S. Vickers
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Publication number: 20160202313Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.Type: ApplicationFiled: October 23, 2015Publication date: July 14, 2016Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
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Patent number: 9361533Abstract: A method of obtaining two orthogonally polarized super-resolution images is provided. A first diffraction-limited image is obtained using horizontally polarized light; a second diffraction-limited image is obtained using vertically polarized light; and, the first and second images are processed so as to yield a convoluted image having super diffraction-limited performance in both dimensions. Enhanced alignment of CAD image to acquired image is facilitated using the horizontally and vertically polarized images.Type: GrantFiled: November 16, 2012Date of Patent: June 7, 2016Assignee: DCG SYSTEMS, INC.Inventors: Keith Serrels, Prasad Sabbineni, James S. Vickers
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Publication number: 20160109513Abstract: An apparatus and method for laser voltage testing of a DUT is disclosed. The system enables laser voltage probing and laser voltage imaging of devices within the DUT. A selected area of the DUT is illuminating a while the DUT is receiving test signals causing certain of the active devices to modulate. Light reflected from the DUT is collected and is converted into an electrical signal. The electrical signal is sampled by an ADC and the output of the ADC is sent to an FPGA. The FPGA operates on the signal so as to provide an output that emulates a spectrum analyzer or a vector analyzer.Type: ApplicationFiled: October 16, 2015Publication date: April 21, 2016Inventor: James S. Vickers
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Publication number: 20160104812Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light-transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light-transparent region, to a circuit on the semiconductor substrate.Type: ApplicationFiled: October 23, 2014Publication date: April 14, 2016Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 9201096Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.Type: GrantFiled: May 16, 2013Date of Patent: December 1, 2015Assignee: DCG SYSTEMS, INC.Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
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Patent number: 8872297Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: GrantFiled: February 28, 2013Date of Patent: October 28, 2014Assignee: Tau-Metrix, Inc.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nadar Pakdaman
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Publication number: 20130334644Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: ApplicationFiled: February 28, 2013Publication date: December 19, 2013Applicant: TAU-METRIX, INC.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Publication number: 20130314116Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.Type: ApplicationFiled: May 16, 2013Publication date: November 28, 2013Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
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Patent number: 8410568Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: GrantFiled: August 25, 2009Date of Patent: April 2, 2013Assignee: Tau-Metrix, Inc.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 8344745Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of test structures located on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: August 31, 2006Date of Patent: January 1, 2013Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Patent number: 7736916Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: June 14, 2007Date of Patent: June 15, 2010Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Patent number: 7723724Abstract: A system is provided for using test structures to evaluate a fabrication of a wafer. The test structures include a combination of device and interconnect elements that are provided on an active region of a die, on the wafer prior to the fabrication of the wafer being completed. The combination of device and interconnect elements include one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics. A power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer. The one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits.Type: GrantFiled: August 21, 2008Date of Patent: May 25, 2010Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Publication number: 20100084729Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: ApplicationFiled: August 25, 2009Publication date: April 8, 2010Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 7605597Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: GrantFiled: November 5, 2007Date of Patent: October 20, 2009Assignee: tau-Metrix, Inc.Inventors: Majid Aghababazadeh, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers
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Patent number: 7492529Abstract: A bi-convex solid immersion lens is disclosed, having a top and bottom convex surfaces. The radius of curvature of the bottom surface is larger than that of the top surface. A conical sloped side-wall connects the top and bottom surface.Type: GrantFiled: May 8, 2007Date of Patent: February 17, 2009Assignee: DCG Systems, Inc.Inventors: Nader Pakdaman, James S. Vickers
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Publication number: 20080315196Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.Type: ApplicationFiled: August 21, 2008Publication date: December 25, 2008Inventors: Majid AGHABABAZADEH, Jose J. Estabil, Nader Pakdaman, Gary L. Steinbrueck, James S. Vickers