Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract: An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.

Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage.

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Abstract: An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology.

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialisation checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Abstract: An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.

Abstract: An interconnect comprising paths configured to transmit data packets between nodes on a network. The nodes comprise ports for inputting and outputting the data packets to the interconnect. At least two of the paths each have at least a portion configured such that a data packet addressed for output at one of the nodes on one of the paths and not being accepted at the node will continue along the path and on travelling further will return to the node. The at least two paths are balanced paths such that a data packet not accepted at the one of the nodes will return to the node a same predetermined number of clock cycles later whichever of the balanced paths the data packet is traveling along.

Abstract: An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology.

Abstract: A system for simulating an engine environment during engine operation is disclosed. The system includes a surface. The system also includes a liquid delivery device configured to deliver a liquid to the surface. The system further includes a temperature controller operably coupled to the surface, and the system is configured to cause condensation of a fluid on the surface.

Abstract: An engine including an oil spray collector is provided. The collector is located on an underside surface of the valve cover to accept a previously identified oil spray from at least one engine component.

Abstract: A system for simulating an engine environment during engine operation is disclosed. The system includes a surface. The system also includes a liquid delivery device configured to deliver a liquid to the surface. The system further includes a temperature controller operably coupled to the surface, and the system is configured to cause condensation of a fluid on the surface.

Abstract: Disclosed is a process for modifying cashew nut shell liquid (CNSL) which involves the steps of subjecting the CNSL to ozonolysis to form ozonolysis reaction products, followed by reduction of the ozonolysis reaction products to give a mixture of phenolic components and aldehydes. In a preferred embodiment, the process involves reacting CNSL with ozone to form a mixture containing ozonolysis reaction products, and then treating the mixture under reducing conditions to form a further mixture containing phenolic components with an eight carbon chain having a terminal —CHO group and alkyl components of varying lengths with either one or two terminal —CHO groups. The resulting CNSL aldehydes may be used to form adhesives for use in the manufacture of composites such as wood particle board.

Abstract: Disclosed is a process for modifying cashew nut shell liquid (CNSL) which involves the steps of subjecting the CNSL to ozonolysis to form ozonolysis reaction products, followed by reduction of the ozonolysis reaction products to give a mixture of phenolic components and aldehydes. In a preferred embodiment, the process involves reacting CNSL with ozone to form a mixture containing ozonolysis reaction products, and then treating the mixture under reducing conditions to form a further mixture containing phenolic components with an eight carbon chain having a terminal —CHO group and alkyl components of varying lengths with either one or two terminal —CHO groups. The resulting CNSL aldehydes may be used to form adhesives for use in the manufacture of composites such as wood particle board.

Abstract: A firmware management method and system provides close control over a firmware development process via a firmware management tool and an archive. The archive can be used to store firmware files containing firmware source code in progress as well as finished source code along with its associated object code. The management tool includes an auditing function and a workflow management function so that the status of each firmware file and the work history of that file can be monitored and stored. By providing a centralized location for firmware source and object code, the tool makes it easier to track and modify firmware code at any stage as well as ensures that the code ultimately sent to a chip manufacturer is the final version of the code.