Patents by Inventor James SCHEUERMANN
James SCHEUERMANN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7809050Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.Type: GrantFiled: October 13, 2009Date of Patent: October 5, 2010Assignee: QST Holdings, LLCInventor: W. James Scheuermann
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Publication number: 20100220706Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: October 28, 2009Publication date: September 2, 2010Inventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20100161940Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: March 8, 2010Publication date: June 24, 2010Applicant: QST Holdings, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20100037029Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: ApplicationFiled: February 9, 2009Publication date: February 11, 2010Applicant: QST HOLDINGS LLCInventors: W. James SCHEUERMANN, Eugene B. HOGENAUER
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Publication number: 20100027597Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.Type: ApplicationFiled: October 13, 2009Publication date: February 4, 2010Applicant: QST HOLDINGS, LLC.Inventor: W. James Scheuermann
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Patent number: 7653710Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: GrantFiled: May 21, 2003Date of Patent: January 26, 2010Assignee: QST Holdings, LLC.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 7620097Abstract: A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.Type: GrantFiled: December 23, 2008Date of Patent: November 17, 2009Assignee: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Patent number: 7620678Abstract: Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine.Type: GrantFiled: June 12, 2003Date of Patent: November 17, 2009Assignee: NVIDIA CorporationInventors: Paul L. Master, W. James Scheuermann
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Publication number: 20090161863Abstract: An integrated circuit for implementing the secure hash algorithm is provided, According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller flirter includes an address control module and a finite state machine.Type: ApplicationFiled: January 14, 2009Publication date: June 25, 2009Applicant: QST HOLDINGS, LLCInventor: Walter James SCHEUERMANN
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Publication number: 20090103594Abstract: A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20090104930Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Patent number: 7506237Abstract: A reconfigurable bit-manipulation node is disclosed that includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit is comprised of interconnected elements that include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.Type: GrantFiled: March 6, 2007Date of Patent: March 17, 2009Assignee: NVIDIA CorporationInventors: Brian Box, John M. Rudosky, Walter James Scheuermann
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Patent number: 7489779Abstract: An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.Type: GrantFiled: March 5, 2002Date of Patent: February 10, 2009Assignee: QSTHoldings, LLCInventor: Walter James Scheuermann
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Publication number: 20090037693Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: Quicksilver Technology, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20090037692Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: Quicksilver Technology, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20090037691Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: Quicksilver Technology, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Method and system for implementing a system acquisition function for use with a communication device
Publication number: 20080247443Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: June 18, 2008Publication date: October 9, 2008Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann -
Patent number: 7433909Abstract: A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric Finite Impulse Response (FIR) Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad Infinite Impulse Response (IIR) Filter, Radix-2 Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), Radix-2 Discrete Cosign Transform (DCT)/Inverse Discrete Cosign Transform (IDCT), Golay Correlator, Local Oscillator/Mixer.Type: GrantFiled: May 21, 2003Date of Patent: October 7, 2008Assignee: NVIDIA CorporationInventor: W. James Scheuermann
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Method and system for implementing a system acquisition function for use with a communication device
Patent number: 7400668Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences-the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: GrantFiled: February 4, 2002Date of Patent: July 15, 2008Assignee: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann -
Publication number: 20080130742Abstract: A video processor uses attributes of video data to perform encoding and decoding. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.Type: ApplicationFiled: May 9, 2005Publication date: June 5, 2008Applicant: QuickSilver Technology, Inc.Inventor: W. James Scheuermann