Abstract: A video processor according to the invention is dynamically configurable as to the attributes of the video data upon which the processor operates. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.

Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.

Abstract: An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An interconnection network is coupled to a second group of computational elements to configures the second group for a second operation.

Abstract: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Abstract: A data distributor in a computational unit of an integrated circuit is enclosed. The data distributor receives data from a network and distributes the data to a plurality of components within the computational unit. The data distributor includes an input mechanism for receiving the data from the network, and distributes the data to a selected component of the plurality of components, a control mechanism responsive to a control signal for distributing the data to the selected component using a data distribution selected between a look-up table-based memory write and a point-to-point distribution with acknowledgement. The plurality of components comprises a Peek/Poke Module, an Execution Unit, a DMA Engine, and a Hardware Task Manager Message Generator. The selected data distribution type may comprise using an output port number or a direct-memory address transfer or an interrupt to distribute the data.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements includes a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up-table memory and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.

Abstract: A computational unit, or node, in an adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric FIR Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad IIR Filter, Radix-2 FFT/IFFT, Radix-2 DCT/IDCT, Golay Correlator, Local Oscillator/Mixer.

Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.

Abstract: Aspects for data flow control of execution nodes of an adaptive computing engine (ACE) are presented. The aspects include associating task parameters with tasks within an execution node. Readiness of task resources is identified based on a status of the task parameters. Subsequently, allocation of the tasks to the execution node occurs based on the readiness of task resources.

Abstract: A computational unit, or node, in an adaptive computing engine uses a uniform interface to a network to communicate with other nodes and resources. The uniform interface is referred to as a “node wrapper.” The node wrapper includes a hardware task manager (HTM), a data distributor, optional direct memory access (DMA) engine and a data aggregator. The hardware task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The HTM coordinates a nodes assigned tasks using a task lists. A “ready-to-run queue” is implemented as a first-in first-out stack. The HTM uses a top-level finite-state machine (FSM) that communicates with a number of subordinate FSMs to control individual HTM components. The Data Distributor interfaces between the node's input pipeline register and various memories and registers within the node.

Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.

Abstract: The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.

Abstract: A fast, memory efficient, lookup table-based system for VLC decoding. Code words are grouped by prefix and recoded to reduce the number of bits that must be matched, thus reducing the memory requirements. General-purpose processor and finite state machine decoder implementations are described.

Abstract: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.

Abstract: A fast, memory efficient, lookup table-based system for VLC decoding. Code words are grouped by prefix and recoded to reduce the number of bits that must be matched, thus reducing the memory requirements. General-purpose processor and finite state machine decoder implementations are described.