Abstract: A buffer/interface device of the memory node may read and compress blocks of data (e.g., pages). When a memory buffer device compresses a block of data, it may keep storing the original uncompressed version in the original memory location (e.g., physical memory page). In this manner, an access directed to the block of data may be satisfied with the uncompressed version retrieved from the original memory location (e.g., physical memory page) without having to perform a decompression operation. As memory space is needed for other purposes (e.g., for an uncompressed copy of a recently decompressed block or as host allocated memory occupies more space), the original uncompressed versions of blocks (pages) that have not been accessed relatively recently (e.g., relative to other kept original uncompressed versions) may be evicted and replaced by other blocks of data (e.g., either compressed or uncompressed).

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract: Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. Based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated.

Abstract: Described are self-learning systems and methods for adaptive management of memory resources within a memory hierarchy. Memory allocations associated with different active functions are organized into blocks for placement in alternative levels in a memory hierarchy optimized for different metrics of e.g. cost and performance. A host processor monitors a performance metric of the active functions, such as the number of instructions per clock cycle, and reorganizes the function-specific blocks among the levels of the hierarchy. Over time, this process tends toward block organizations that improve the performance metric.

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract: Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. Based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated.

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract: Described are self-learning systems and methods for adaptive management of memory resources within a memory hierarchy. Memory allocations associated with different active functions are organized into blocks for placement in alternative levels in a memory hierarchy optimized for different metrics of e.g. cost and performance. A host processor monitors a performance metric of the active functions, such as the number of instructions per clock cycle, and reorganizes the function-specific blocks among the levels of the hierarchy. Over time, this process tends toward block organizations that improve the performance metric.

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract: A sensing device projects near-field spatial modulations onto a closely spaced photodetector array. Due to physical properties of the grating, the point-spread response distributes spatial modulations over a relatively large area on the array. The spatial modulations are captured by the array, and photographs and other image information can be extracted from the resultant data. An image-change detector incorporating such a sensing device uses very little power because only a small number of active pixels are required to cover a visual field.

Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

Abstract: A memory address and a virtual cache identifier are received in association with a request to retrieve data from a cache data array. Context information is selected based on the virtual cache identifier, the context information indicating a first region of a plurality of regions within the cache data array. A cache line address that includes a first number of bits of the memory address in accordance with a size of the first region is generated and, if the cache data array is determined to contain, in a location indicated by the cache line address, a cache line corresponding to the memory address, the cache line is retrieved from the location indicated by the cache line address.

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.