SELECTIVE REFRESH WITH SOFTWARE COMPONENTS
A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.
This application is a Continuation of U.S. patent Ser. No. 13/975,873, filed Aug. 26, 2013, entitled SELECTIVE REFRESH WITH SOFTWARE COMPONENTS, which claims the benefit of priority under 35 U.S.C. 119(e) to Provisional Application Ser. No. 61/693,911, filed Aug. 28, 2012, entitled SELECTIVE REFRESH WITH SOFTWARE COMPONENTS, which are incorporated by reference in their entirety for all purposes.
TECHNICAL FIELDThe disclosure herein relates to memory systems, and more specifically to methods and apparatus for memory refresh operations.
BACKGROUNDMemory systems typically employ large amounts of DRAM memory as main memory. At the transistor level, a DRAM cell is a capacitor structure, with the capability of maintaining a charge representing a “bit” on the order of approximately 64 mS. To maintain the charge, the cell needs to be periodically refreshed—generally involving a read and write operation every 64 mS. Conventionally, the entire DRAM array is blindly refreshed even though much of the memory may not be active. Conventional refresh operations can consume as much as a third of the power consumption associated with the memory.
While DRAMs traditionally employ hardware-based refresh operations at very high rates, a variety of other memory technologies provide fast access times similar to DRAM, but with much slower refresh rate requirements. For example, some forms of RRAM can operate with refresh rates on the order of seconds. Slower refresh rates can also be beneficial for memory technologies that are susceptible to repetitive write operations that can degrade cell retention.
Thus, the need exists for an improved refresh scheme for memory systems that can minimize power dissipation and take advantage of reduced-rate refresh requirements.
Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Embodiments of methods and apparatus for refreshing a memory are disclosed. In one embodiment, a method of refreshing a memory includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria. In this manner, low-power selective refresh operations may be successfully carried out by a software-based refresh scheme.
In a further embodiment, a method of managing memory refresh operations is disclosed. The method involves a first mode of operation that includes generating an active memory map of the memory with software. The active memory map has addresses corresponding to active memory allocated by the software, and is stored in a location within the active memory. The stored active memory map is accessed to evaluate refresh criteria for a portion of the active memory. Based on the refresh criteria, an operation to refresh a portion of the active memory is initiated. Other embodiments include a self-refresh mode of operation in addition to the first mode of operation where externally generated refresh instructions are not issued to refresh the memory.
Another embodiment presented herein relates to a memory device that includes storage cells operable to store an active memory map. Software generates the active memory map which identifies addresses of active memory in the memory device. In a first refresh mode of operation, the storage cells are operable, in response to refresh commands based on operations initiated by the software, to selectively refresh a portion of the active memory corresponding to the active memory map. In a second mode of operation, the storage cells are operable, in response to self-refresh commands, to selectively refresh a portion of the active memory corresponding to a loaded bitmap version of the active memory map.
In yet a further embodiment, a memory controller is disclosed that includes a host interface, decoder circuitry, and a memory interface. The host interface is operable to receive refresh instructions that are based on an active memory map of a memory. The active memory map being generated by operating system software under control of a host device. The decoder circuitry generates memory device address-specified refresh command signals based on the refresh instructions. The memory interface issues the refresh command signals to the memory to carry out selective refresh operations based on the active memory map.
To address the various possible memory configurations, a software-based memory manager is often used to monitor and map how the physical memory is allocated within the computing system's total memory. The portion of the system memory realized by the main memory 102 usually includes a quickly accessible collection of volatile memory devices, while the bulk memory 104 often takes the form of a hard disc 104 or other mass media storage device.
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The memory array 210 in one embodiment takes the form of one or more integrated circuit memory devices. Data associated with the allocated page table 214 is stored in a portion of the memory array 210 as an active memory map 216. The memory devices are formed in accordance with memory cell technology that provides storage cells which exhibit relatively long retention times. In specific embodiments, the retention times are at least 650 ms. More generally, the retention time is of a duration longer than a time interval necessary to allow the operating system software 212 to issue refresh instructions to the memory controller 208 to subsequently issue refresh commands to the memory devices to refresh the active memory in the memory array 210 based on the retrieved map.
In addition to allowing for refresh operations managed by the external operating system software 212, each memory device includes self-refresh hardware 218, explained in further detail below, to allow each memory device to enter and exit a low-power self-refresh mode of operation. When this mode is initiated, information based on the active memory map 216 is bitmapped into bitmap portions of each device for access by each memory device during self-refresh. Selective self-refresh operations are then enabled to refresh only those portions of active memory in each memory device, as mapped by the bitmapping. Further details regarding this mode of operation are explained in the text that follows.
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Following the refresh operation, the operating system software 212 determines whether the self-refresh mode 307 should be initiated based on predetermined self-refresh criteria, at step 314. If the self-refresh mode 307 is not initiated, then the next standard refresh operation begins with a subsequent access of the active memory map 216 at step 306. If the self-refresh mode 307 is initiated, at step 314, then the active memory map 216 is copied to a portion of each memory device, at step 316, and a hardware-based self-refresh scheme employed. In one embodiment, this includes, for example, a state machine on each memory device to selectively refresh the portion of the memory array 210 corresponding to the loaded memory map, at step 318.
Once the highest priority entry in the allocated page list 402 decrements its refresh status count to zero (or some other predetermined threshold), a refresh manager 408 detects the condition and generates refresh instructions for the allocated page in terms of its virtual memory space. The instructions are sent to a memory controller 410 (such as the controller corresponding to the memory controller 208 in
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In many situations, the operating system software 212 will update the system memory usage such that new pages may be added to allocated memory.
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Once the memory commands are generated, the memory controller 410 schedules the commands into appropriate queues and issues the commands to the one or more memory devices 414 corresponding to the page, at step 710. The addressed portions of the one or more memory devices are then refreshed in response to the commands, at step 712. Should the system initiate a self-refresh mode of operation, further refresh instructions initiated by the operating system software are halted, and instead, refresh activities are carried out solely on the memory devices 414 as more fully described with respect to
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In one embodiment, the refresh hardware 802 interfaces with a bitmap portion 804 of each memory device 414. The bitmap portion stores a bitmap representation of the active memory map (such as 216,
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Those skilled in the art will appreciate the benefits and advantages afforded by the embodiments described herein. Selectively refreshing only those memory locations that are allocated to active memory provides significant power savings due to reductions in refresh current. Moreover, handling selective refresh via a software-based scheme that tracks the allocated memory reduces implementation costs and complexity. By providing ways to selectively refresh active memory in both standard and self-refresh modes, further power savings may be realized.
When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘
While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims
1. (canceled)
2. A method of refreshing allocated portions of a memory, the method comprising:
- sorting the allocated portions to determine a highest priority portion of the allocated portions, the sorting based on a refresh status parameter associated with the allocated portions;
- tracking the refresh status parameter of the highest priority portion; and
- scheduling a refresh instruction for the highest priority portion based on the tracked refresh status parameter reaching a threshold value.
3. The method of claim 2, wherein:
- the allocated portions each represent a page of memory storage locations corresponding to a page address.
4. The method of claim 2, wherein:
- the refresh status parameter associated with the highest priority portion comprises a count value representing expiration of a retention time associated with the highest priority portion.
5. The method of claim 4, wherein the tracking comprises:
- initiating a page operation;
- decrementing the count value in response to the initiating;
- determining whether the decremented count reaches the threshold value; and
- iteratively repeating the initiating, decrementing and determining until the count reaches the threshold.
6. The method of claim 2 wherein sorting and tracking are carried out by operating system software.
7. The method of claim 2 wherein the scheduling is carried out by operating system software.
8. The method of claim 2, further comprising:
- after scheduling the refresh instruction, sorting the highest priority portion as a lowest priority portion.
9. A method, comprising:
- prioritizing refresh operations for a memory device, the prioritizing including identifying active portions of the memory device as allocated portions; associating the allocated portions with a refresh status parameter; sorting the allocated portions to determine a highest priority portion of the allocated portions, the sorting based on the refresh status parameter associated with the allocated portions; tracking the refresh status parameter of the highest priority portion; and scheduling a refresh instruction for the highest priority portion based on the tracked refresh status parameter reaching a threshold value.
10. The method of claim 9 wherein:
- the allocated portions each represent a page of memory storage locations corresponding to a page address.
11. The method of claim 9, wherein:
- the refresh status parameter associated with the highest priority portion comprises a count value representing expiration of a retention time associated with the highest priority portion.
12. The method of claim 11, wherein the tracking comprises:
- initiating a page operation;
- decrementing the count value in response to the initiating;
- determining whether the decremented count reaches the threshold value; and
- iteratively repeating the initiating, decrementing and determining until the count reaches the threshold.
13. The method of claim 9 wherein sorting and tracking are carried out by operating system software.
14. The method of claim 9 wherein the scheduling is carried out by operating system software.
15. The method of claim 9, further comprising:
- after scheduling the refresh instruction, sorting the highest priority portion as a lowest priority portion.
16. A refresh controller for prioritizing refresh operations for allocated portions of a memory, the refresh controller comprising:
- a tracking module including a sorter to sort the allocated portions to determine a highest priority portion of the allocated portions, the sort based on a refresh status parameter associated with the allocated portions, and a tracker to track the refresh status parameter of the highest priority portion; and
- a refresh manager in communication with the tracker to schedule a refresh instruction for the highest priority portion based on the tracked refresh status parameter reaching a threshold value.
17. The refresh controller of claim 16, wherein:
- the allocated portions each represent a page of memory storage locations corresponding to a page address.
18. The refresh controller of claim 16, wherein:
- the refresh status parameter associated with the highest priority portion comprises a count value representing expiration of a retention time associated with the highest priority portion.
19. The refresh controller of claim 18, wherein:
- the tracker is operative to initiate a page operation; decrement the count value in response to the initiating; determine whether the decremented count reaches the threshold value; and iteratively repeat the initiate, decrement and determine until the count reaches the threshold.
20. The refresh controller of claim 16, wherein:
- the sorter and the tracker are controlled by operating system software.
21. The method of claim 16 wherein:
- the refresh manager is controlled by operating system software.
Type: Application
Filed: Dec 6, 2018
Publication Date: Jun 27, 2019
Inventors: Hongzhong Zheng (Sunnyvale, CA), James Tringali (Los Altos, CA), Frederick A. Ware (Los Altos Hills, CA)
Application Number: 16/211,956