Patents by Inventor James V. Russell

James V. Russell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9153890
    Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 6, 2015
    Assignee: R+DCircuits, Inc.
    Inventors: Thomas P Warwick, James V Russell, Demick McMullim, William Quick
  • Patent number: 9107330
    Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: August 11, 2015
    Assignee: R&D Sockets, Inc.
    Inventor: James V Russell
  • Publication number: 20150096873
    Abstract: A shuttle board relay is provided that is scalable to a specific pitch or routing density. The shuttle board relay provides a path with different sets of electrical components that allows this via by allowing the integration of components and other types of customization. The shuttle board relay provides a minimally disruptive path to the signal. This minimizes loss and signal distortion, isolation and crosstalk are a function of pitch. Since pitch can be set, grounds included, etc., a design may be fully optimized for low cross talk.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: R&D Circuits, Inc.
    Inventors: Thomas P. Warwick, James V. Russell
  • Publication number: 20150027749
    Abstract: A method and structure for improving signal integrity probing. A coaxial or a microcoaxial cable is threaded through an optional alignment substrate where the cable is used to support or align the cable or an array of cables. A conductive elastomer is placed on a cable or a microcoaxial cable to improve signal integrity probing.
    Type: Application
    Filed: October 13, 2014
    Publication date: January 29, 2015
    Applicant: R&D Sockets, Inc.
    Inventors: Thomas P. Warwick, James V. Russell
  • Patent number: 8848385
    Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 30, 2014
    Assignee: R&D Sockets, Inc
    Inventors: Thomas P. Warwick, James V. Russell
  • Publication number: 20140283379
    Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.
    Type: Application
    Filed: June 6, 2014
    Publication date: September 25, 2014
    Applicant: R&D Circuits, Inc.
    Inventor: James V. Russell
  • Publication number: 20140268613
    Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.
    Type: Application
    Filed: April 30, 2014
    Publication date: September 18, 2014
    Applicant: R&D Circuits,Inc.
    Inventor: James V. Russell
  • Patent number: 8792248
    Abstract: The present invention provides a method for embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blind vias are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. With this methodology a resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: July 29, 2014
    Assignee: R & D Circuits, Inc.
    Inventor: James V Russell
  • Patent number: 8743554
    Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 3, 2014
    Assignee: R & D Circuits, Inc.
    Inventor: James V. Russell
  • Publication number: 20140069704
    Abstract: A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.
    Type: Application
    Filed: July 25, 2013
    Publication date: March 13, 2014
    Applicant: R&D Circuits, Inc.
    Inventors: Dan Turpuseema, James V. Russell
  • Publication number: 20130280929
    Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 24, 2013
    Inventors: Thomas P. Warwick, James V. Russell, Demick McMullim, William Quick
  • Publication number: 20130240247
    Abstract: A method and structure for improving signal integrity probing. A coaxial or a microcoaxial cable is threaded through an optional alignment substrate where the cable is used to support or align the cable or an array of cables. A conductive elastomer is placed on a cable or a microcoaxial cable to improve signal integrity probing.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 19, 2013
    Applicant: R & D Circuits, Inc.
    Inventors: Thomas P. Warwick, James V. Russell
  • Patent number: 8354601
    Abstract: A method and a structure for a coaxial via that extend along the entire length of a signal via in a printed circuit board. Signal integrity is improved by providing ground shield for the entire length of the coaxial via. The ground shielding can be implemented by either providing ground cage vias around a signal via and routing a trace to the signal via on a built up layer or by providing a semi circle ground trench through a build up layer to permit a trace access to the signal via.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: January 15, 2013
    Inventor: James V. Russell
  • Publication number: 20120285011
    Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.
    Type: Application
    Filed: June 22, 2012
    Publication date: November 15, 2012
    Applicant: R&D Circuits, Inc.
    Inventor: James V. Russell
  • Publication number: 20120081867
    Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.
    Type: Application
    Filed: September 28, 2011
    Publication date: April 5, 2012
    Applicant: R&D Circuits, Inc.
    Inventors: Thomas P. Warwick, James V. Russell
  • Publication number: 20120048593
    Abstract: A looped conductive wire or alternatively a conductive material such as a conductive foil is electrically connected with elastomeric material to provide electrical connections with one or more electronic devices.
    Type: Application
    Filed: July 29, 2011
    Publication date: March 1, 2012
    Applicant: R&D Circuits, Inc.
    Inventor: James V. Russell
  • Patent number: 8066517
    Abstract: An electrical connector using an isotropic conductive elastomer as the interconnect medium.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 29, 2011
    Inventor: James V. Russell
  • Publication number: 20110223780
    Abstract: An electrical connector electrically connects either an adaptor board or an electrical component to a main circuit board through the use of a thin printed circuit having an array of pads one each side where on one side the pads are connected to a main circuit board by solder balls, solder columns conductive epoxy or any other way practiced in the art and on the other side of the thin circuit the pads are connected to an adaptor board by a conductive compliant elastomeric material. The sides of the thin printed circuit are electrically connected to one another in ways practiced in the art.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 15, 2011
    Inventor: James V. Russell
  • Publication number: 20110203842
    Abstract: A method and a structure for a coaxial via that extend along the entire length of a signal via in a printed circuit board. Signal integrity is improved by providing ground shield for the entire length of the coaxial via. The ground shielding can be implemented by either providing ground cage vias around a signal via and routing a trace to the signal via on a built up layer or by providing a semi circle ground trench through a build up layer to permit a trace access to the signal via.
    Type: Application
    Filed: March 31, 2010
    Publication date: August 25, 2011
    Inventor: James V. Russell
  • Publication number: 20110155792
    Abstract: The present disclosure provides for scoring a line on metal to form a solder dam to define a solderable area on a metal surface. The solderable area can define solderable pads on a solid copper plane or at the end point of a trace on a circuit board. The present disclosure provides for soldering metallic surfaces together and for aligning solderable objects to one another. The surface tension of solder enables the parts to be aligned through the manipulations of the skived patterns and their placement. The skiving can be done either by laser skiving or by mechanical scoring on the metallic surfaces.
    Type: Application
    Filed: March 31, 2010
    Publication date: June 30, 2011
    Inventor: James V. Russell