Abstract: An improved method and structure is provided for constructing elastomeric pin arrays using a non-conductive medium and compression limiters. Pin to pin of the same elastomeric material, pin to pin of similar elastomeric material, or pin to metal cap structure interconnects are constructed using an elastomeric connection through a non-conductive medium. Compression limiting structures are mated to the non-conductive medium. This structure eliminates the need for PCB structures as the medium reducing manufacturing cost.

Abstract: An improved method and structure is provided for constructing elastomeric pin arrays using a non-conductive medium and compression limiters. Pin to pin of the same elastomeric material, pin to pin of similar elastomeric material, or pin to metal cap structure interconnects are constructed using an elastomeric connection through a non-conductive medium. Compression limiting structures are mated to the non-conductive medium. This structure eliminates the need for PCB structures as the medium reducing manufacturing cost.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: The present invention relates to a method and an apparatus for a resurfaceable contact pad that uses an epoxy to encapsulate contact pads so that the epoxy and encapsulated contact pads are coplanar on a silicon redistribution interposer. These redistribution interposers electrically connect a wafer semi-conductor to a probe card where it is necessary to convert the course pad arrangement of one with a fine pad arrangement of the other through the use of an interposer board. The present invention relates to an apparatus and a method creates resurfaceable contact pads which may be resurfaced one or multiple times with an abrasive sanding operation to recreate a coplanar surface should any contact pad surfaces become damaged, allowing for a more cost-effective repair.

Abstract: The present invention relates to a method and an apparatus for a resurfaceable contact pad that uses an epoxy to encapsulate contact pads so that the epoxy and encapsulated contact pads are coplanar on a silicon redistribution interposer. These redistribution interposers electrically connect a wafer semi-conductor to a probe card where it is necessary to convert the course pad arrangement of one with a fine pad arrangement of the other through the use of an interposer board. The present invention relates to an apparatus and a method creates resurfaceable contact pads which may be resurfaced one or multiple times with an abrasive sanding operation to recreate a coplanar surface should any contact pad surfaces become damaged, allowing for a more cost-effective repair.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads.

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract: A method and structure is provided for constructing elastomeric pin arrays using solder interconnects and a non-conductive medium. Pin to pin interconnects are constructed using a solder connection through a non-conductive medium. This structure eliminates the need for PCB structures as the medium, reducing manufacturing cost. In another embodiment one or more elastomeric columns extend through holes or openings in the non conductive medium. The elastomeric columns are fixed securely within the holes preferably with adhesive material. Compression stops are provided on both sides of each elastomeric column for both the upper and bottom surfaces of the non conductive medium.

Abstract: A method and structure for improving signal integrity probing. A coaxial or a microcoaxial cable is threaded through an optional alignment substrate where the cable is used to support or align the cable or an array of cables. A conductive elastomer is placed on a cable or a microcoaxial cable to improve signal integrity probing.

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

Abstract: A method and an apparatus for connecting a coaxial (or a micro coaxial) cable to the bottom side of a printed circuit board (PCB) in order to improve signal integrity of a test circuit. A coaxial or a micro coaxial cable is directly connected to a coaxial cable to the bottom sides of pads located on an exterior later of the PCB.

Abstract: A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.

Abstract: A shuttle board relay is provided that is scalable to a specific pitch or routing density. The shuttle board relay provides a path with different sets of electrical components that allows this via by allowing the integration of components and other types of customization. The shuttle board relay provides a minimally disruptive path to the signal. This minimizes loss and signal distortion, isolation and crosstalk are a function of pitch. Since pitch can be set, grounds included, etc., a design may be fully optimized for low cross talk.

Abstract: A method and a structure with multiple implementations is provided that depends on the specific need, for placing (embedding) a serial loopback circuit of known design in a printed circuit board directly beneath the device under test. Micro-vias and traces connect components including transmitter components (TX) and receiver components (RX) that are formed into a loopback circuit for connection to a device under test (DUT). The connection is accomplished by a coupling capacitor with a shortest possible electrical length approximating a straight line between said components and said DUT and said distance is a length of said short straight line times a square root of 2 so that said receiver components are beneath the DUT.

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component.

Abstract: A method and structure is provided for constructing elastomeric pin arrays using solder interconnects and a non-conductive medium. Pin to pin interconnects are constructed using a solder connection through a non-conductive medium. This structure eliminates the need for PCB structures as the medium, reducing manufacturing cost. In another embodiment a non conductive medium has holes therein and serves as a compression stop. One or more first elastomeric column is formed on an upper side of a conductive disc. The conductive disc is fixedly adhered to a pad located on an underside of the non conductive medium aligned so that the one or more first elastomeric column extends through said holes of the non conductive medium. One or more second elastomeric column is formed on an underside or bottom of the conductive medium or disc.