Abstract: A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.

Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract: A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

Abstract: Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter.

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are provided herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter.

Abstract: Switchable and/or tunable filters and methods of manufacture. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.

Abstract: Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g.

Abstract: Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material.

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract: Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically connected one to another and to the first conductive plate. The supercapacitor may also include a dielectric formed on surfaces of the 3D aggregate of sintered nanoparticles. The supercapacitor may further include a second electrode comprising a solid second conductor that fills interstices between surfaces of the dielectric and electrically connects to a second conductive plate of a solid second conductor, disposed above an outermost portion of the dielectric.

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.