Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module includes a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus.

Abstract: Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.

Abstract: Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.

Abstract: Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.

Abstract: A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.

Abstract: Systems and methods, for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.

Abstract: Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.

Abstract: BIOS instructions are transferred from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.

Abstract: A system transfers BIOS instructions from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.

Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.

Abstract: The present invention relates to a computer system comprising at least one requesting agent, a system controller and a memory subsystem comprising a main memory and a noncacheable subset of main memory physically distinct from the main memory.

Abstract: A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.