Abstract: A method and system for representing an electronic device having input-output ports and test circuits associated with the input-output ports includes: receiving a functional level description of the electronic device; determining a connectivity relationship between a first test circuit associated with a first input-output port and a second test circuit associated with a second input-output port; and generating a functional level representation of the determined connectivity relationship. Functional level descriptions include hardware description languages such as VHDL and VERILOG.

Abstract: A method of checking data integrity in a computer system which includes the acts of: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.

Abstract: The present invention relates to a computer system comprising at least one requesting agent, a system controller and a memory subsystem comprising a main memory and a noncacheable subset of main memory physically distinct from the main memory.

Abstract: A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The cache controller receives a configuration signal having first and second states, with the configuration signal of the first state configuring the cache controller to monitor and control a direct-mapped cache, and the configuration signal of the second state configuring the cache controller to monitor and control a two-way set-associative cache. The cache controller includes first and second comparators, each able to compare respective first and second cache tags to a memory address. Both of the comparators are enabled when monitoring cache hits to a two-way set-associative cache, whereas only one of the comparators is enabled when monitoring a direct-mapped cache. The cache controller also includes first and second control circuits, each receiving a hit signal produced by a respective one of the comparators.

Abstract: The present invention relates to a method in a computer system, for configuring a memory subsystem, comprising selecting a subset of main memory, integrating the subset of main memory within the computer system such that the subset is physically distinct from the main memory and configuring the subset of main memory as noncacheable memory.

Abstract: A system and process for invalidating addresses within a cache memory system is described. The system and process allow a set-associative cache memory system in a computer to simultaneously analyze all sets corresponding to a particular address to determine whether the data at a particular address needs to be written back to the computer's main memory. A set of flags is stored with each address in the cache memory so that the flags can be scrutinized to determine whether the data stored in that set is valid, but not modified.

Abstract: A lenticular image product comprising: a lenticular material having an array of lenticules with cylindrical lenses; and a lenticular image associated with the lenticular material, the lenticular image having an original image having a wide angle view and at least one final image having a narrow angle view created from the original image, such that tilting of the lenticular image product produces a zoom effect between the original and final images.

Abstract: A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The system employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P6 bus. The system further comprises a third device, electrically connected to the P6 bus, which communicates the request having a defer enable signal to the target.

Abstract: A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The cache controller receives a configuration signal having first and second states, with the configuration signal of the first state configuring the cache controller to monitor and control a direct-mapped cache, and the configuration signal of the second state configuring the cache controller to monitor and control a two-way set-associative cache. The cache controller includes first and second comparators, each able to compare respective first and second cache tags to a memory address. Both of the comparators are enabled when monitoring cache hits to a two-way set-associative cache, whereas only one of the comparators is enabled when monitoring a direct-mapped cache. The cache controller also includes first and second control circuits, each receiving a hit signal produced by a respective one of the comparators.

Abstract: A lenticular image product comprising: a lenticular material having an array of lenticules with cylindrical lenses; and a lenticular image associated with the lenticular material, the lenticular image having an original image having a wide angle view and at least one final image having a narrow angle view created from the original image, such that tilting of the lenticular image product produces a zoom effect between the original and final images.

Abstract: A method of communication between requester and target devices in a computer system having a multiple bus architecture. The method supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The method employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The method comprises the act of establishing a handshake with a host master and issuing a request over the host bus. The method further comprises the act of acknowledging the request and transmitting a deferred response to the requester.

Abstract: A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

Abstract: A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The system employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P6 bus. The system further comprises a third device, electrically connected to the P6 bus, which communicates the request having a defer enable signal to the target.

Abstract: An IDE controller having an IDE interface that includes a primary channel for transmitting primary data from a primary device and a secondary channel for transmitting secondary data from a secondary device; a primary CRC circuit for receiving the primary data, performing an operation on the primary data and generating primary CRC values; a secondary CRC circuit for receiving the secondary data, performing an operation on the secondary data and generating secondary CRC values, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; and a compare circuit for comparing the primary CRC values with the secondary CRC values and generating compare values.

Abstract: An apparatus for testing an IDE controller with random constraints, the apparatus including: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes at least one channel and a host interface; a control module for generating data patterns and for transmitting and receiving the data patterns via the host interface and the at least one channel; a verification module, coupled to the control module, for determining whether received data patterns match expected values; and a device module, coupled to the at least one channel, for receiving the data patterns transmitted from the control module and transmitting the data patterns back to the verification module via the at least one channel.

Abstract: A method of checking data integrity in a computer system which includes the acts of: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.

Abstract: A system provides for direct transfer of data from one mass storage device, such as a hard disk drive, to another storage device, through an EIDE controller. Data from one disk drive, on one of the primary or secondary EIDE channels, is routed through the EIDE controller, to another disk drive on the other EIDE channel. The EIDE controller employs a pair of multiplexers and block move buses that allow data to be selectively routed between the primary and secondary EIDE channels. The processor in a host PC need only initialize the transfer with a few commands. Thereafter, the EIDE controller performs all block data transfers between the hard disk drives, without additional processor involvement.

Abstract: A system provides for direct transfer of data from one mass storage device, such as a hard disk drive, to another storage device, through an EIDE controller. Data from one disk drive, on one of the primary or secondary EIDE channels, is routed through the EIDE controller, to another disk drive on the other EIDE channel. The EIDE controller employs a pair of multiplexers and block move buses that allow data to be selectively routed between the primary and secondary EIDE channels. The processor in a host PC need only initialize the transfer with a few commands. Thereafter, the EIDE controller performs all block data transfers between the hard disk drives, without additional processor involvement.

Abstract: An apparatus for testing an IDE controller with random constraints, the apparatus including: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes primary and secondary channels and a host interface; a primary control module, coupled to the host interface, for testing the primary channel; a secondary control module, coupled to the host interface, for testing the secondary channel; and a host request module for arbitrating access to the host interface between the primary and secondary control modules.

Abstract: A simple rangefinder device, suitable for two-zone ranging applications, comprises a single lens, a light emitter located with respect to the lens to produce a beam of light, and a light detector located with respect to the lens to define a field of view. The effective lens aperture for the emitter and the detector substantially coincide and the field of view of the detector overlaps the light beam in a detection region extending away from the lens for a predetermined distance. Signal processing electronics receive a signal produced by the light detector to produce a signal representing the presence or absence of a reflecting object in the detection region.