Patents by Inventor James Waugh

James Waugh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10061728
    Abstract: A device for selecting requests to be serviced in a data processing apparatus has an arbitration stage for selecting an arbitrated request from a plurality of candidate requests and a hazard detection stage for performing hazard detection to predict whether the arbitrated request selected by the arbitration stage meets a hazard condition. If the arbitrated request meets the hazard condition, the hazard detection stage returns the arbitration request to the arbitration stage for a later arbitration and sets a hazard indication for the returned request. Also, the hazard detection stage controls at least one other arbitration request to be returned if it conflicts with a candidate request having the hazard indication set. This approach prevents denial of service to requests that were hazarded.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 28, 2018
    Assignee: ARM Limited
    Inventor: Alex James Waugh
  • Publication number: 20180225214
    Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL, Klas Magnus BRUCE, Michael FILIPPO, Paul Gilbert MEYER, Alex James WAUGH, Geoffray Matthieu LACOURBA
  • Publication number: 20180225216
    Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Alex James WAUGH, Geoffray LACOURBA, Paul Gilbert MEYER, Bruce James MATHEWSON, Phanindra Kumar MANNAVA
  • Patent number: 9823256
    Abstract: There is provided a molecular marker CXCR1 for predicting response and survival in subjects afflicted with cancer who would benefit from treatment with and Epidermal Growth Factor Receptor (EGFR) targeted therapeutic.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 21, 2017
    Assignee: The Queen's University of Belfast
    Inventors: David John James Waugh, Richard Wilson, Olabode Oladipo
  • Publication number: 20170293567
    Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Richard F. BRYANT, Kim Richard SCHUTTENBERG, Lilian Atieno HUTCHINS, Thomas Edward ROBERTS, Alex James WAUGH, Max John BATLEY
  • Publication number: 20170228318
    Abstract: An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups.
    Type: Application
    Filed: December 28, 2016
    Publication date: August 10, 2017
    Inventors: Davide MARANI, Alex James WAUGH
  • Publication number: 20170109289
    Abstract: An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data processing operations on data, and a virtually indexed, physically tagged cache for storing data for access by the processing circuitry. The cache is accessed using a virtual address portion of a virtual address in order to identify a number of cache entries, and then physical address portions stored in those cache entries are compared with the physical address derived from the virtual address in order to detect whether a hit condition exists.
    Type: Application
    Filed: September 21, 2016
    Publication date: April 20, 2017
    Inventors: Jose GONZALEZ GONZALEZ, Alex James WAUGH, Adnan KHAN
  • Publication number: 20170091113
    Abstract: There is provided a data processing apparatus comprising: processing circuitry to speculatively execute an instruction referencing a virtual address. Lookup circuitry receives the virtual address from the processing circuitry. The lookup circuitry comprises storage circuitry to store at least one virtual address and page walking circuitry to perform a page walk on further storage circuitry, in dependence on the virtual address being unlisted by the storage circuitry, to determine whether a correspondence between a physical address and the virtual address exists. The lookup circuitry signals an error when the correspondence cannot be found and, in response to the error being signaled, the storage circuitry stores an entry comprising the virtual address.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventor: Alex James WAUGH
  • Publication number: 20170091097
    Abstract: An apparatus comprises a translation lookaside buffer (TLB) comprising TLB entries for storing address translation data for translating virtual addresses to physical addresses. Hazard checking circuitry detects a hazard condition when two data access transactions correspond to the same physical address. The hazard checking circuitry includes a TLB entry identifier comparator to compare TLB entry identifiers identifying the TLB entries corresponding to the two data access transactions. The hazard condition is detected in dependence on whether the TLB entry identifiers match.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 30, 2017
    Inventors: Alex James WAUGH, Max John BATLEY, Thomas Edward ROBERTS
  • Publication number: 20170076758
    Abstract: There is provided an apparatus comprising power state determination circuitry to determine a power state of a processing circuit; and control circuitry to issue a control signal relating to an item of data stored in a first storage circuitry. When the power state of the processing circuit is a predetermined state, the control circuitry issues a further control signal to a second storage circuitry to indicate whether the item of data is to be retained by the second storage circuitry.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 16, 2017
    Inventor: Alex James WAUGH
  • Publication number: 20170060175
    Abstract: An apparatus includes control circuitry configured to receive a first N-bit count value in a first domain, and to determine an M-bit increment indicating value based on the first N-bit count value and a reference value, where M<N. Boundary circuitry is configured to provide the M-bit increment indicating value to a second domain. In the second domain, updating circuitry configured to update a second N-bit count value based on an increment represented by the M-bit increment indicating value provided by the boundary circuitry.
    Type: Application
    Filed: August 3, 2016
    Publication date: March 2, 2017
    Inventor: Alex James WAUGH
  • Publication number: 20160048469
    Abstract: A device for selecting requests to be serviced in a data processing apparatus has an arbitration stage for selecting an arbitrated request from a plurality of candidate requests and a hazard detection stage for performing hazard detection to predict whether the arbitrated request selected by the arbitration stage meets a hazard condition. If the arbitrated request meets the hazard condition, the hazard detection stage returns the arbitration request to the arbitration stage for a later arbitration and sets a hazard indication for the returned request. Also, the hazard detection stage controls at least one other arbitration request to be returned if it conflicts with a candidate request having the hazard indication set. This approach prevents denial of service to requests that were hazarded.
    Type: Application
    Filed: July 17, 2015
    Publication date: February 18, 2016
    Inventor: Alex James WAUGH
  • Patent number: 9242596
    Abstract: A vehicle or trailer side marker and/or downlight (10) includes a casing or housing (1) and adjustable mounting (4,5), an internal reflector an internal baffle or shield, a light source, a lens or diffuser cover to allow adjustment of beam orientation, direction or angular spread to determine ground spread and beam upper margin limits so as not to dazzle others.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: January 26, 2016
    Inventor: James Waugh Thomson
  • Patent number: 9003123
    Abstract: An instruction cache stores cacheable instructions for access by a processing circuitry, the instruction cache having a data storage comprising a plurality of cache lines and a tag storage comprising a plurality of tag entries, each cache line for storing instruction data specifying a plurality of cacheable instructions, and each tag entry for storing an address identifier for the instruction data stored in an associated cache line. The instruction cache including valid flag storage for identifying whether each cache line is valid. Instruction cache control circuitry is arranged to store within a selected cache line of the data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 7, 2015
    Assignee: ARM Limited
    Inventors: Alex James Waugh, Matthew Lee Winrow
  • Patent number: 8977820
    Abstract: A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of an error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. A clean and invalidate operation is performed in respect of the specific cache line, and the access request is then re-performed. Cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from a lookup procedure.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: March 10, 2015
    Assignee: ARM Limited
    Inventors: Antony John Penton, Alex James Waugh, Andrew Christopher Rose, Paul Stanley Hughes
  • Publication number: 20140313756
    Abstract: A vehicle or trailer side marker and/or downlight (10) includes a casing or housing (1) and adjustable mounting (4,5), an internal reflector an internal baffle or shield, a light source, a lens or diffuser cover to allow adjustment of beam orientation, direction or angular spread to determine ground spread and beam upper margin limits so as not to dazzle others.
    Type: Application
    Filed: October 19, 2012
    Publication date: October 23, 2014
    Inventor: James Waugh Thomson
  • Patent number: D707833
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 24, 2014
    Inventors: Anna Waugh, Neil James Waugh
  • Patent number: D711178
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 19, 2014
    Assignee: The Snap Organisation USA Inc
    Inventor: James Waugh
  • Patent number: D714457
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 30, 2014
    Inventors: Anna Waugh, Neil James Waugh
  • Patent number: D744262
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: December 1, 2015
    Inventors: Anna Waugh, Neil James Waugh