Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.

Abstract: A pin electronics circuit for use in automatic testing equipment that includes a load for testing a pin of a device under test. The load of the pin electronics circuit is electrically coupled to a precision parametric measurement unit. In this embodiment, the precision pin measurement unit provides a forcing signal to the load when a high current mode is desired. In response to the forcing signal, the load generates a current through a resistor that results in a desired current or voltage at a pin of the device under test. Since the load is used in high current mode, the precision parametric measurement unit does not include a high current output stage.

Abstract: In one embodiment of the invention, a switchable output current mirror with feedback is disclosed. The current mirror includes a master stage, a slave stage, and an operational amplifier that is coupled in a feedback loop with the master stage. A reference current is introduced at an input node of the current mirror. The input node is coupled to an input terminal of the operational amplifier and to a current source of the master stage. The output of the operational amplifier electrically couples to the master stage to control the current source of the master stage. The slave stage of the current mirror includes a current source that receives the output from the output terminal of the operational amplifier to control the current source. The slave stage also includes a switch for receiving a control signal and selectively coupling the current source of the slave stage with the output of the current mirror. The master stage may include a switch that is controllable by a control signal.

Abstract: A circuit operating as a bridgeless current load in pin testing equipment for testing a pin of a device under test is disclosed. The circuit includes a transconductance stage having at least a first input and a second input and at least one output capable of being coupled to a pin of a device under test. The circuit further includes a first limiting current source coupled to the transconductance stage for sourcing the pin of the device under test to a first current level and a second limiting current source coupled to the transconductance stage for sinking the pin of the device under test to a second current level. The first input receives a commutation voltage and the second input receives a voltage at the output of the transconductance stage from the device under test. When the output voltage is above the commutation voltage, the first limiting current source is active and when the output voltage is below the commutation voltage, the second limiting current source is active.