Abstract: An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

Abstract: A centralised synchronizing device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system. A system synchronizing request is a request generated by one of the plurality of transaction generating devices and queries progress of a subset of the transaction requests. The synchronizing device includes: at least one port to and from the data processing system; a multicast circuitry configured to output a plurality of synchronizing requests for multicast to at least some of the devices within the data processing system where the requests query the progress of the subset of the transaction requests. Gather circuitry collects responses to the requests confirming that the queried progress has occurred at the respective devices. The gather circuitry determines when responses to all of the requests have been received and outputs a response to the system synchronizing request.

Abstract: Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device.

Abstract: An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

Abstract: A centralised synchronising device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system in response to receipt of a system synchronising request, the data processing system having a plurality of devices including a plurality of transaction request generating devices for generating the transaction requests and a plurality of recipient devices for receiving the transaction requests, the synchronising device and at least one interconnect for interconnecting at least some of the devices; wherein the system synchronising request comprising a request generated by one of the plurality of transaction generating devices and querying progress of the at least a subset of the transaction requests; the synchronising device comprising: at least one port for receiving requests from, and outputting requests and responses to, the data processing system; multicast circuitry configured to generate a plurality of synchronising requests in response to recei

Abstract: A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.

Abstract: An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

Abstract: A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. The data processing system process write requests in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data it responds to the first part and the data and state of the data prior to the write are sent as a second part of the write request. When there are copending reads and writes to the same address the writes are stalled by the coherency controller by not responding to the first part of the write and the initiator device proceeds to process any snoop requests received to the address of the write regardless of the fact that the write is pending. When the pending read has completed the coherency controller will respond to the first part of the write and the initiator device will complete the write by sending the data and an indicator of the state of the data following the snoop.

Abstract: Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device.

Abstract: A data processing apparatus 2 includes a plurality of transaction sources 8, 10 each including a local cache memory. A shared cache memory 16 stores cache lines of data together with shared cache tag values. Snoop filter circuitry 14 stores snoop filter tag values tracking which cache lines of data are stored within the local cache memories. When a transaction is received for a target cache line of data, then the snoop filter circuitry 14 compares the target tag value with the snoop filter tag values and the shared cache circuitry 16 compares the target tag value with the shared cache tag values. The shared cache circuitry 16 operates in a default non-inclusive mode. The shared cache memory 16 and the snoop filter 14 accordingly behave non-inclusively in respect of data storage within the shared cache memory 16, but inclusively in respect of tag storage given the combined action of the snoop filter tag values and the shared cache tag values.

Abstract: A system (10) uses shared resources (44, 54) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (42, 52, 48). A reload buffer (44, 54) is used in conjunction with a cache (42, 52) operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal (70) selectively enables the pushing of data into the cache (42, 52, 48) from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.

Abstract: A system (10) uses shared resources (44, 54) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (42, 52, 48). A reload buffer (44, 54) is used in conjunction with a cache (42, 52) operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal (70) selectively enables the pushing of data into the cache (42, 52, 48) from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.

Abstract: A system (10) uses shared resources (44, 54) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (42, 52, 48). A reload buffer (44, 54) is used in conjunction with a cache (42, 52) operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal (70) selectively enables the pushing of data into the cache (42, 52, 48) from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.

Abstract: A system (10) uses shared resources (44, 54) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (42, 52, 48). A reload buffer (44, 54) is used in conjunction with a cache (42, 52) operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal (70) selectively enables the pushing of data into the cache (42, 52, 48) from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.