Patents by Inventor Jan Hoentschel

Jan Hoentschel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10644152
    Abstract: One illustrative integrated circuit product disclosed herein includes at least one transistor formed on an active region of on an SOI substrate, the transistor comprising a gate that includes a gate structure, first and second source/drain regions positioned on opposite sides of the gate, the first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type, and a doped region positioned below the gate, wherein the doped region has a lateral width that is at least substantially equal to the CPP (contact-poly-pitch) dimension of the transistor and is doped with a dopant material of the first type, wherein a first portion of the doped region is positioned vertically above an interface between the active region and a buried insulation layer of the SOI substrate and a second portion of the doped region is positioned vertically below the interface.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Luca Pirro, Tom Herrmann, El Mehdi Bazizi, Jan Hoentschel
  • Publication number: 20200083346
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: George Robert MULFINGER, Ryan SPORER, Rick J. CARTER, Peter BAARS, Hans-Jürgen THEES, Jan HÖNTSCHEL
  • Patent number: 10580863
    Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel, Lars Mueller-Meskamp, Martin Gerhardt
  • Patent number: 10522655
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Rick J. Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel
  • Patent number: 10386406
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Otto, Jan Höntschel, Maximilian Jüttner
  • Publication number: 20190242939
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 8, 2019
    Inventors: Michael OTTO, Jan HÖNTSCHEL, Maximilian JÜTTNER
  • Patent number: 10340380
    Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Ralf Richter, Peter Javorka
  • Patent number: 10283490
    Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Jan Hoentschel, Alexander Ebermann
  • Publication number: 20190109192
    Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 11, 2019
    Inventors: Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel, Lars Mueller-Meskamp, Martin Gerhardt
  • Patent number: 10157996
    Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Patent number: 10056376
    Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Patent number: 9960184
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
  • Patent number: 9917087
    Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Stefan Flachowksy, Juergen Faul, Jan Hoentschel
  • Patent number: 9881841
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Alban Zaka, Ran Yan, El Mehdi Bazizi, Jan Hoentschel
  • Publication number: 20180012973
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Inventors: George Robert MULFINGER, Ryan SPORER, Rick J. CARTER, Peter BAARS, Hans-Jürgen THEES, Jan HÖNTSCHEL
  • Publication number: 20180012877
    Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: Sven Beyer, Jan Hoentschel, Alexander Ebermann
  • Publication number: 20170345914
    Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.
    Type: Application
    Filed: July 13, 2017
    Publication date: November 30, 2017
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Publication number: 20170330953
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: George Robert MULFINGER, Ryan SPORER, Rick J. CARTER, Peter BAARS, Hans-Jürgen THEES, Jan HÖNTSCHEL
  • Publication number: 20170317108
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.
    Type: Application
    Filed: July 10, 2017
    Publication date: November 2, 2017
    Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
  • Patent number: 9806170
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Rick J. Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel