Patents by Inventor Jan-Willem van de Waerdt
Jan-Willem van de Waerdt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8732409Abstract: A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.Type: GrantFiled: November 16, 2009Date of Patent: May 20, 2014Assignee: Entropic Communications, Inc.Inventors: Pieter Van Der Wolf, Abraham Karel Riemens, Jan-Willem Van de Waerdt
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Publication number: 20140022185Abstract: Apparatuses and methods of synchronizing a display driver integrated circuit (DDI) and a touch screen controller (TSC) integrated circuit that are coupled to a display integrated touch panel, such as an in-cell panel, and allowing multi-phase transmit (TX) scanning of the in-cell touch panel. One apparatus includes a DDI configured to receive signals on a video interface from a host processor over a video interface and to drive electrodes of a touch panel. The DDI is configured to receive control signals from a TSC over a control interface to drive different transmit (TX) phase sequences of a TX signal in different sensing interval on the electrodes of the touch panel.Type: ApplicationFiled: November 15, 2012Publication date: January 23, 2014Inventors: Milton Ribeiro, Bart DeCanne, Jan-Willem Van de Waerdt
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Publication number: 20140022211Abstract: Capacitive touch sensors and touchscreen data processing methods are provided. In one embodiment, the method includes sequentially integrating and converting charge from each of a plurality of sensing capacitors in an array to digital data, the digital data including sample values corresponding to a measured capacitance for each of the plurality of sensing capacitors. Noise is then separated from useful information by filtering the sample values on a sample-by-sample basis. Finally, the filtered sample values are summed and a position of at least one contact on the array determined using the filtered capacitance values. Other embodiments are also provided.Type: ApplicationFiled: September 5, 2013Publication date: January 23, 2014Applicant: Cypress Semiconductor CorporationInventors: Oleksandr Karpin, Igor Kolych, Andriy Maharyta, lhor Musijchuk, Victor Kremin, Jan-Willem van de Waerdt
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Publication number: 20140022206Abstract: A contact's interaction with a sensing array is subject to several external and internal stimuli which may impact a processing unit's confidence in the characteristics of that interaction or the presence of the interaction itself. Fidelity of user action is greatly improved with a step-wise and holistic analysis of a contact on an array of capacitance sensors, which allows for repetition of certain steps of processing or the entire operation if threshold confidence levels are not achieved.Type: ApplicationFiled: March 14, 2013Publication date: January 23, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventor: Jan-Willem van de Waerdt
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Patent number: 8607026Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.Type: GrantFiled: November 17, 2011Date of Patent: December 10, 2013Assignee: Nytell Software LLCInventors: Paulus Stravers, Jan-Willem van de Waerdt
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Patent number: 8418092Abstract: A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source-synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).Type: GrantFiled: November 27, 2008Date of Patent: April 9, 2013Assignee: NXP B.V.Inventors: Carlos Basto, Jan-Willem Van De Waerdt
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Patent number: 8379715Abstract: A system and method for video compression utilizes non-linear quantization and modular arithmetic computation to perform differential coding on multiple blocks of video data and uses a result of the differential coding to generate a codeword.Type: GrantFiled: August 27, 2009Date of Patent: February 19, 2013Assignee: NXP B. V.Inventor: Jan-Willem Van De Waerdt
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Patent number: 8239631Abstract: A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory.Type: GrantFiled: April 24, 2009Date of Patent: August 7, 2012Assignee: Entropic Communications, Inc.Inventors: Jan-Willem van de Waerdt, Johan Gerard Willem Maria Janssen, Maurice Penners
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Publication number: 20120066475Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.Type: ApplicationFiled: November 17, 2011Publication date: March 15, 2012Applicant: NYTELL SOFTWARE LLCInventors: Paulus Stravers, Jan-Willem van de Waerdt
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Patent number: 7975093Abstract: A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.Type: GrantFiled: October 18, 2006Date of Patent: July 5, 2011Assignee: NXP B.V.Inventors: Jan-Willem Van De Waerdt, Carlos Basto
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Publication number: 20110051802Abstract: A system and method for video compression utilizes non-linear quantization and modular arithmetic computation to perform differential coding on multiple blocks of video data and uses a result of the differential coding to generate a codeword.Type: ApplicationFiled: August 27, 2009Publication date: March 3, 2011Applicant: NXP B.V.Inventor: Jan-Willem Van De Waerdt
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Publication number: 20100274974Abstract: A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: NXP B.V.Inventors: JAN-WILLEM VAN DE WAERDT, JOHAN GERARD WILLEM MARIA JANSSEN, MAURICE PENNERS
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Publication number: 20100271084Abstract: A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source-synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).Type: ApplicationFiled: November 27, 2008Publication date: October 28, 2010Applicant: NXP B.V.Inventors: Carlos Basto, Jan-Willem Van de Waerdt
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Publication number: 20100077151Abstract: A computer system includes a data cache supported by a copy-back buffer and pre-allocation request stack. A programmable trigger mechanism inspects each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated. If the store operation memory address occurs within a range defined by START and END programmable registers, then the next cache line that includes a memory address within that defined by a programmable STRIDE register is requested for pre-allocation. Bunches of pre-allocation requests are organized and scheduled by the pre-allocation request stack, and will take their turns to allow the cache lines being replaced to be processed through the copy-back buffer. By the time the processor gets to doing the store operation in the next cache line, such cache line has already been pre-allocated and there will be a cache hit, thus saving stall cycles.Type: ApplicationFiled: January 24, 2008Publication date: March 25, 2010Applicant: NXP, B.V.Inventor: Jan Willem Van De Waerdt
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Publication number: 20100050164Abstract: Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.Type: ApplicationFiled: December 11, 2007Publication date: February 25, 2010Applicant: NXP, B.V.Inventors: Jan-Willem Van De Waerdt, Steven Roos
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Publication number: 20100005274Abstract: A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor “Virtual” views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those types of functional units that are too difficult or too costly to physically duplicate. By providing different virtual views to the different clusters of a VLIW processor, the compiler/scheduler can generate more efficient code for the processor, than a processor without virtual views and the physical unit restricted to a subset of the processor's clusters. The compiler/scheduler guarantees that the restrictions with respect to scheduling of operations for functional units with multiple virtual views is met. NON-clustered processors also benefit from virtual views.Type: ApplicationFiled: December 11, 2007Publication date: January 7, 2010Applicant: NXP, B.V.Inventor: Jan-Willem Van De Waerdt
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Publication number: 20090217004Abstract: A prefetch bit (126) is associated with cache block (125) of a cache (120), and the management (130) of cache-prefetch operations is based on the state of this bit (126). Further efficiencies are gained by allowing each application to identify memory areas (115) within which regularly repeating memory accesses are likely, such as frame memory in a video application. For each of these memory areas (115), the application also identifies a likely stride value, such as the line length of the data in the frame memory. Pre-fetching is limited to the identified areas (115), and the prefetch bit (126) is used to identify blocks (125) from these areas and to limit repeated cache hit/miss determinations.Type: ApplicationFiled: November 15, 2005Publication date: August 27, 2009Applicant: Koninkliijke Phillips Electronics N.V.Inventors: Jan-Willem Van De Waerdt, Jean-Paul Vanitegem
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Publication number: 20080209129Abstract: A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.Type: ApplicationFiled: October 18, 2006Publication date: August 28, 2008Applicant: NXP B.V.Inventors: Jan-Willem Van De Waerdt, Carlos Basto
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Patent number: 7406569Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.Type: GrantFiled: August 12, 2002Date of Patent: July 29, 2008Assignee: NXP B.V.Inventor: Jan-Willem van de Waerdt
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Patent number: 7353337Abstract: Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the instructions contained in the instruction cache prior to execution of the ISR are overwritten by the ISRs instructions. To reduce trashing of the instruction cache memory, the instruction cache is dynamically partitioned into a first memory portion and a second memory portion during execution. The first memory portion is for storing instructions of the current instruction stream, and the second memory portion is for storing instructions of the ISR. Thus, the ISR only affects the second memory portion and leaves instruction data stored within the first memory portion intact. This partitioning of the instruction cache reduces processor fetch operations as well as reduces power consumption of the instruction cache memory.Type: GrantFiled: February 23, 2004Date of Patent: April 1, 2008Assignee: NXP B.V.Inventors: Rogier Wester, Jan-Willem Van De Waerdt, Gert Slavenburg