Patents by Inventor Jane A. Yater

Jane A. Yater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6839280
    Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gowrishankar L. Chindalore, Rajesh A. Rao, Jane A. Yater
  • Publication number: 20040266107
    Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventors: Gowrishankar L. Chindalore, Rajesh A. Rao, Jane A. Yater
  • Patent number: 6791883
    Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: September 14, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Craig T. Swift, Jane A. Yater, Alexander B. Hoefler, Ko-Min Chang, Erwin J. Prinz, Bruce L. Morton
  • Patent number: 6751125
    Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: June 15, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erwin J. Prinz, Craig T. Swift, Jane A. Yater, Sung-Wei Lin, Frank K. Baker, Jr.
  • Publication number: 20040085815
    Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Inventors: Erwin J. Prinz, Craig T. Swift, Jane A. Yater, Sung-Wei Lin, Frank K. Baker
  • Publication number: 20030235083
    Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
    Type: Application
    Filed: June 24, 2002
    Publication date: December 25, 2003
    Inventors: Craig T. Swift, Jane A. Yater, Alexander B. Hoefler, Ko-Min Chang, Erwin J. Prinz, Bruce L. Morton
  • Patent number: 5889287
    Abstract: A reversible thermoelectric converter includes first and second quantum well diodes and an electrical connection between the first and second quantum well diodes without a thermal barrier between them. Each quantum well diode includes first and second electrodes wherein electrons are quantized in discrete energy levels and a dielectric layer providing a potential barrier between the first and second electrodes. When electrons in the first quantum well diode have a higher temperature than the electrons in the second quantum well diode, electric voltage fluctuations resulting from transitions of the electrons between the energy levels in the first quantum well diode are coupled from the first quantum well diode to the second quantum well diode. The reversible thermoelectric converter can be operated for power conversion of thermal energy to electric energy, as a heat pump or a refrigerator, or as an amplifier.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: March 30, 1999
    Inventors: Joseph C. Yater, Jane A. Yater, Joan E. Yater
  • Patent number: 5623119
    Abstract: A reversible thermoelectric converter includes first and second quantum well diodes and an electrical connection between the first and second quantum well diodes without a thermal barrier between them. Each quantum well diode includes first and second electrodes wherein electrons are quantized in discrete energy levels and a dielectric layer providing a potential barrier between the first and second electrodes. When electrons in the first quantum well diode have a higher temperature than the electrons in the second quantum well diode, electric voltage fluctuations resulting from transitions of the electrons between the energy levels in the first quantum well diode are coupled from the first quantum well diode to the second quantum well diode. The reversible thermoelectric converter can be operated for power conversion of thermal energy to electric energy, as a heat pump or a refrigerator, or as an amplifier.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: April 22, 1997
    Inventors: Joseph C. Yater, Jane A. Yater, Joan E. Yater
  • Patent number: 5470395
    Abstract: A reversible thermoelectric converter includes first and second quantum well diodes and an electrical connection between the first and second quantum well diodes without a thermal barrier between them. Each quantum well diode includes first and second electrodes wherein electrons are quantized in discrete energy levels and a dielectric layer providing a potential barrier between the first and second electrodes. When electrons in the first quantum well diode have a higher temperature than the electrons in the second quantum well diode, electric voltage fluctuations resulting from transitions of the electrons between the energy levels in the first quantum well diode are coupled from the first quantum well diode to the second quantum well diode. The reversible thermoelectric converter can be operated for power conversion of thermal energy to electric energy, as a heat pump or a refrigerator, or as an amplifier.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: November 28, 1995
    Inventors: Joseph C. Yater, Jane A. Yater, Joan E. Yater
  • Patent number: 5356484
    Abstract: A reversible thermoelectric converter includes first and second quantum well diodes and an electrical connection between the first and second quantum well diodes without a thermal barrier between them. Each quantum well diode includes first and second electrodes wherein electrons are quantized in discrete energy levels and a dielectric layer providing a potential barrier between the first and second electrodes. When electrons in the first quantum well diode have a higher temperature than the electrons in the second quantum well diode, electric voltage fluctuations resulting from transitions of the electrons between the energy levels in the first quantum well diode are coupled from the first quantum well diode to the second quantum well diode. The reversible thermoelectric converter can be operated for power conversion of thermal energy to electric energy, as a heat pump or a refrigerator, or as an amplifier.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: October 18, 1994
    Inventors: Joseph C. Yater, Jane A. Yater, Joan E. Yater