Patents by Inventor Jane Sowards

Jane Sowards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180083096
    Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 22, 2018
    Applicant: Xilinx, Inc.
    Inventors: Jing Jing, Shuxian Wu, Jane Sowards
  • Patent number: 9923051
    Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 20, 2018
    Assignee: XILINX, INC.
    Inventors: Jing Jing, Shuxian Wu, Jane Sowards
  • Publication number: 20050040850
    Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.
    Type: Application
    Filed: July 23, 2004
    Publication date: February 24, 2005
    Applicant: Xilinx, Inc.
    Inventors: David Schultz, Stephen Douglass, Steven Young, Nigel Herron, Mehul Vashi, Jane Sowards