SUBSTRATE NOISE ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES
An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.
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Examples of the present disclosure generally relate to electronic circuits and, in particular, to substrate noise isolation structures for semiconductor devices.
BACKGROUNDSilicon integrated circuits (ICs) suffer from substrate coupling because the substrates are not good insulators. Coupling electric signals between circuits through the semiconductor substrate can cause noise interference and affect the normal function of the circuits. Thus, reducing unwanted substrate noise is important to ensure the normal function and performance of ICs with silicon substrates in both bulk and Fin Field Effect Transistor (FinFET) technologies.
Various techniques have been employed in ICs to reduce substrate coupling. One technique is to add high-resistance paths in the substrate. Another technique is to add guard rings around sensitive circuits. For bulk complementary metal oxide semiconductor (CMOS) technologies, the guard rings are continuous, which forms good isolation between circuits. For FinFET technologies, however, the guard rings are no longer continuous in the vertical direction and the oxide definition (OD) width is limited by the maximum Fin numbers in each FinFET technology. In this case, substrate noise can leak through the gaps in the guard rings and cause unwanted noise and interference. The inventors have found the substrate noise to be 30 dB higher in cases of a discontinuous guard ring. As technology advances, the substrate coupling becomes more severe, since the distance between circuits becomes smaller.
SUMMARYTechniques for providing substrate noise isolation structures for semiconductor devices. In an example, a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.
In another example, a method of manufacturing a semiconductor device includes: forming a first circuit and a second circuit in a semiconductor substrate; forming a first guard structure in the semiconductor substrate between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis; and forming a second guard structure in the semiconductor substrate between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.
These and other aspects may be understood with reference to the following detailed description.
So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples.
DETAILED DESCRIPTIONVarious features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described.
Techniques for substrate noise isolation structures for semiconductor devices are provided. The disclosed techniques greatly reduce substrate noise induced by circuits in integrated circuits (ICs) that include Fin Field Effect Transistors (FinFETs). In an example, multiple oxide definition (OD) guard rings of N+/P+ types with a shifted pattern are used to implement a substrate noise isolation scheme. The isolation scheme can be placed between circuit blocks as a wall, or can surround circuit blocks, to suppress substrate noise coupling. These and further aspects are described below with respect to the drawings.
The substrate noise isolation structure 105 is disposed between the noise source circuit 102 and the noise receiver circuit 104. In the present example, the substrate noise isolation structure 105 forms a wall between the circuits 102, 104. In other examples (described below), the substrate noise isolation structure 105 can be implemented as one or more rings surrounding one of the circuits 102, 104. The substrate noise isolation structure 105 is configured to reduce substrate coupling between the circuits 102, 104. For example, as shown in
The substrate noise isolation structure 105 includes a plurality of guard structures 106. In the example, guard structures 106-1 and 106-2 are formed in the semiconductor substrate 101. Each guard structure 106 comprises a column of discrete diffusion regions extending along a Y-axis of an X-Y plane of the semiconductor substrate 101. As shown, the diffusion regions of the guard structures 106 are discontinuous along the Y-axis. For example, for FinFET technologies, the oxide definition (OD) width is limited by the maximum Fin numbers in each FinFET technology. Thus, it is not possible to form continuous diffusion regions along the axis of the OD width (e.g., the Y-axis).
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Techniques for substrate noise isolation structures for semiconductor devices have been described. In general, a substrate noise isolation structure between two circuits includes at least two guard structures having discontinuous pairs of n+ and p+ diffusions. Between two guard structures, the discontinuous pairs of n+ and p+ diffusions are staggered so that the gaps therebetween are not aligned. The guard structures can be walls between the circuits or sides of guard rings surrounding one of the circuits. The described techniques provide for improved substrate noise isolation, particularly in technologies where continuous diffusion regions cannot be formed along at least one dimension of the substrate. For example, in FinFET technologies, the width of the OD is limited based on the maximum Fin number of the technology, which prevents the formation of continuous diffusion regions along one axis.
The examples described above are capable of different variations. In the examples above, the lengths along the X-axis of the n+ and p+ diffusions in the discrete n+/p+ pairs are substantially the same. In other examples, for a given n+/p+ diffusion pair, the length along the X-axis of the n+ diffusion can be different than the length along the X-axis of the p+ diffusion. In the examples described above, the widths along the Y-axis of the n+ and p+ diffusions in the discrete n+/p+ pairs are substantially the same (e.g., a maximum width as determined by the maximum OD width). In other examples, the width of one n+/p+ pair can be different than the width of another n+/p+ pair in the same guard structure or across different guard structures. In general, the width of an n+/p+ pair is at least as wide as a gap between n+/p+ pairs of an adjacent guard structure.
While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims
1. A semiconductor device, comprising:
- a first circuit and a second circuit formed in a semiconductor substrate;
- a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions of substantially the same size disposed along a first axis; and
- a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions of substantially the same size disposed along the first axis and adjacent to the first discontinuous pairs of n+ and p+ diffusions along a second axis perpendicular to the first axis, each second discontinuous pair of n+ and p+ diffusions overlapping two of the first discontinuous pairs of n+ and p+ diffusions.
2. The semiconductor device of claim 1, wherein the first guard structure includes a first continuous diffusion extending along the second axis perpendicular with the first axis, and the second guard structure includes a second continuous diffusion extending along the second axis.
3. The semiconductor device of claim 2, wherein the first guard structure is a first guard ring formed around the first circuit, the first guard ring including first and second sides formed by respective first and second sets of the first discontinuous n+ and p+ diffusions and second and third sides formed by respective first and second portions of the first continuous diffusion.
4. The semiconductor device of claim 3, wherein the second guard structure is a second guard ring formed around the first guard ring, the second guard ring including first and second sides formed by respective first and second sets of the second discontinuous n+ and p+ diffusions and second and third sides formed by respective first and second portions of the second continuous diffusion.
5. The semiconductor device of claim 1, further comprising:
- a moat between the first discontinuous pairs of n+ and p+ diffusions and the second discontinuous pairs of n+ and p+ diffusions.
6. The semiconductor device of claim 1, further comprising:
- a deep well formed in the semiconductor substrate and disposed between the first discontinuous pairs of n+ and p+ diffusions and the second discontinuous pairs of n+ and p+ diffusions.
7. The semiconductor device of claim 1, wherein the semiconductor substrate comprises a p-type substrate, and wherein the first and second guard structures are formed in the p-type substrate.
8. The semiconductor device of claim 1, wherein a well is formed in the substrate, and wherein the first and second guard structures are formed in the well.
9. The semiconductor device of claim 1, wherein the first discontinuous pairs of n+ and p+ diffusions include first gaps and the second discontinuous pairs of n+ and p+ diffusions include second gaps, and wherein the first gaps are not aligned along a second axis perpendicular to the first axis.
10. The semiconductor device of claim 1, wherein, for each of the first discontinuous pairs of n+ and p+ diffusions, the n+ diffusion is staggered with respect to the p+ diffusion.
11. The semiconductor device of claim 1, further comprising:
- a third guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the third guard structure including third discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the third discontinuous pairs of n+ and p+ diffusions being staggered with respect to the second discontinuous pairs of n+ and p+ diffusions.
12. A method of manufacturing a semiconductor device, comprising:
- forming a first circuit and a second circuit in a semiconductor substrate;
- forming a first guard structure in the semiconductor substrate between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions of substantially the same size disposed along a first axis; and
- forming a second guard structure in the semiconductor substrate between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions of substantially the same size disposed along the first axis and adjacent to the first discontinuous pairs of n+ and p+ diffusions along a second axis perpendicular to the first axis, each second discontinuous pair of n+ and p+ diffusions overlapping two of the first discontinuous pairs of n+ and p+ diffusions.
13. The method of claim 12, wherein the first guard structure includes a first continuous diffusion extending along the second axis perpendicular with the first axis, and the second guard structure includes a second continuous diffusion extending along the second axis.
14. The method of claim 13, wherein the first guard structure is a first guard ring formed around the first circuit, the first guard ring including first and second sides formed by respective first and second sets of the first discontinuous n+ and p+ diffusions and second and third sides formed by respective first and second portions of the first continuous diffusion.
15. The method device of claim 14, wherein the second guard structure is a second guard ring formed around the first guard ring, the second guard ring including first and second sides formed by respective first and second sets of the second discontinuous n+ and p+ diffusions and second and third sides formed by respective first and second portions of the second continuous diffusion.
16. The method of claim 12, further comprising:
- forming a moat between the first discontinuous pairs of n+ and p+ diffusions and the second discontinuous pairs of n+ and p+ diffusions.
17. The method of claim 12, further comprising:
- forming a deep well in the semiconductor substrate and disposed between the first discontinuous pairs of n+ and p+ diffusions and the second discontinuous pairs of n+ and p+ diffusions.
18. The method of claim 12, wherein the semiconductor substrate comprises a p-type substrate, and wherein the first and second guard structures are formed in the p-type substrate.
19. The method of claim 12, wherein a well is formed in the substrate, and wherein the first and second guard structures are formed in the well.
20. The method of claim 12, wherein the first discontinuous pairs of n+ and p+ diffusions include first gaps and the second discontinuous pairs of n+ and p+ diffusions include second gaps, and wherein the first gaps are not aligned along a second axis perpendicular to the first axis.
Type: Application
Filed: Sep 21, 2016
Publication Date: Mar 22, 2018
Applicant: Xilinx, Inc. (San Jose, CA)
Inventors: Jing Jing (San Jose, CA), Shuxian Wu (San Jose, CA), Jane Sowards (Fremont, CA)
Application Number: 15/272,292