Patents by Inventor Jang Chen

Jang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250250672
    Abstract: A method of manufacturing a metal nitride film is performed by at least one atomic layer deposition (ALD) cycle. Each of the at least one ALD cycle is firstly to perform at least one half cycle associated with a metal element, and in each half cycle, a precursor containing the metal element is supplied into a reaction chamber, and then a purge gas is selectively supplied into a reaction chamber, where a device is placed. Subsequently, a hydrogen plasma is firstly supplied into the reaction chamber, and then a nitrogen plasma is supplied into the reaction chamber. Alternatively, a nitrogen plasma is firstly supplied into the reaction chamber, and then a hydrogen plasma is supplied into the reaction chamber.
    Type: Application
    Filed: January 17, 2025
    Publication date: August 7, 2025
    Inventor: Miin-Jang CHEN
  • Patent number: 12382705
    Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: August 5, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Sheng-Han Yi, Chen-Hsuan Lu
  • Patent number: 12342728
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 12322742
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: June 3, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Publication number: 20250142919
    Abstract: A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
  • Patent number: 12276875
    Abstract: A display apparatus and a display holding device thereof are provided. The display holding device includes a front frame and a rear plate. The front frame includes an edge portion, a top portion, a containing portion, an extending portion, and a holding portion. The top portion is connected to the edge portion. An end of the containing portion is connected to the edge portion, and the containing portion is adapted to contain an optical transceiver module. The extending portion adapted to contain a panel module is connected to an another end of the containing portion and extends toward a direction away from the edge portion. The holding portion adapted to contain a light-transmissive element is between the containing portion and the extending portion. The rear plate adapted to contain an optical film module is connected to the front frame. Therefore, a width of the front frame can be further reduced.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: April 15, 2025
    Assignee: WISTRON CORPORATION
    Inventors: Chun-Lei Zhao, Yao-Chen Yang, Chia-Jang Chen, Chih-Chou Chou
  • Publication number: 20250105111
    Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive layer and second conductive layer. The second conductive layer is disposed opposite to the first conductive layer. One of the first conductive layer and the second conductive layer includes a first grounding net and a first signal ball-pad. The first grounding net has a first ground void, and the first signal ball-pad is disposed in the first ground void. The first signal ball-pad has a first ball-pad diameter, the first ground void has a first ground void diameter, and a ratio of the first ground void diameter to the first ball-pad diameter is equal to or greater than 1.2.
    Type: Application
    Filed: September 23, 2024
    Publication date: March 27, 2025
    Inventor: Nan-Jang Chen
  • Patent number: 12253251
    Abstract: A casing assembly includes a casing and a light emitting module. The casing is provided with an accommodation recess formed by an inner wall surface and a light outlet portion formed by two inner peripheral edges. The accommodation recess communicates with the light outlet portion. The light emitting module is disposed in the accommodation recess of the casing and located close to the light outlet portion. The light emitting module is provided with a light emitting surface, and a normal line of the light emitting surface is non-parallel and non-perpendicular to an opening direction of the light outlet portion.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: March 18, 2025
    Assignee: WISTRON CORP.
    Inventors: Bin Luo, Ruihua Wang, Zhiyi Liang, chia-jang Chen, chih chou Chou
  • Publication number: 20250087482
    Abstract: A device includes gate spacers, a gate dielectric layer, and one or more gate metals. The gate spacers are over a substrate. The gate dielectric layer is between the gate spacers. The gate dielectric layer includes a horizontal portion extending parallel to a top surface of the substrate, and vertical portions extending upwards from the horizontal portion. A first one of the vertical portions has a thickness less than a thickness of the horizontal portion.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Patent number: 12224334
    Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: February 11, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying Lee, Tse-An Chen, Tzu-Chung Wang, Miin-Jang Chen, Yu-Tung Yin, Meng-Chien Yang
  • Publication number: 20250020952
    Abstract: A display apparatus and a display holding device thereof are provided. The display holding device includes a front frame and a rear plate. The front frame includes an edge portion, a top portion, a containing portion, an extending portion, and a holding portion. The top portion is connected to the edge portion. An end of the containing portion is connected to the edge portion, and the containing portion is adapted to contain an optical transceiver module. The extending portion adapted to contain a panel module is connected to an another end of the containing portion and extends toward a direction away from the edge portion. The holding portion adapted to contain a light-transmissive element is between the containing portion and the extending portion. The rear plate adapted to contain an optical film module is connected to the front frame. Therefore, a width of the front frame can be further reduced.
    Type: Application
    Filed: September 8, 2023
    Publication date: January 16, 2025
    Inventors: Chun-Lei ZHAO, Yao-Chen YANG, Chia-Jang CHEN, Chih-Chou CHOU
  • Patent number: 12191144
    Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Publication number: 20240404877
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Application
    Filed: July 25, 2024
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
  • Publication number: 20240395933
    Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Miin-Jang CHEN, Po-Hsien CHENG, Yu-tung YIN
  • Publication number: 20240397836
    Abstract: A method includes following steps. A bottom electrode layer is formed over a substrate. A first deposition sequence is performed over the bottom electrode layer. The first deposition sequence comprises pulsing a first precursor over the bottom electrode layer such that the first precursor comprises a first plurality of precursor molecules adsorbing on the bottom electrode layer, performing a first purge after pulsing the first precursor, performing a first plasma treating step using a first treatment gas, wherein the first treatment gas reacts with the first plurality of precursor molecules to form a first monolayer of a film, the film has an Al—N bond with a first intensity, pulsing the first treatment gas, and after pulsing the first treatment gas, performing a second plasma treating step using a second treatment gas such that the film has an Al—N bond with a second intensity.
    Type: Application
    Filed: September 25, 2023
    Publication date: November 28, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chen-Hsiang LING, Miin-Jang CHEN
  • Publication number: 20240334847
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Publication number: 20240313060
    Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Inventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
  • Patent number: 12033850
    Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: July 9, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Patent number: 12010933
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Patent number: 11996451
    Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 28, 2024
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin