Patents by Inventor Jang Chen
Jang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120409Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.Type: ApplicationFiled: November 30, 2023Publication date: April 11, 2024Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
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Publication number: 20240102162Abstract: A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.Type: ApplicationFiled: February 1, 2023Publication date: March 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chun-Yi CHOU, Chih-Piao CHUU, Miin-Jang CHEN
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Publication number: 20240088255Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Miin-Jang CHEN, Sheng-Han YI, Chen-Hsuan LU
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Publication number: 20240088124Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Patent number: 11923359Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: GrantFiled: July 12, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shu Wu, Shu-Uei Jang, Wei-Yeh Tang, Ryan Chia-Jen Chen, An-Chyi Wei
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Patent number: 11923350Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.Type: GrantFiled: December 13, 2022Date of Patent: March 5, 2024Assignee: Unimicron Technology Corp.Inventors: Ming-Ru Chen, Tzyy-Jang Tseng, Cheng-Chung Lo
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Publication number: 20240053790Abstract: A monitor includes a casing assembly, a light-emitting module and a display panel. The casing assembly includes a casing and a support frame. The support frame is disposed in the casing. The support frame includes an accommodation portion and at least one support portion, the accommodation portion is connected to the casing, the support portion is connected to the accommodation portion and protrudes from the accommodation portion. The light-emitting module is disposed in the accommodation portion. The display panel is supported by the at least one support portion.Type: ApplicationFiled: December 21, 2022Publication date: February 15, 2024Inventors: CHUNLEI ZHAO, Liang Yang, YAO-CHEN YANG, chia-jang Chen, chih chou Chou
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Patent number: 11903121Abstract: A printed circuit board includes a reference plane embedded in a substrate and adjacent to the top surface of the substrate. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer on the top surface of the substrate covers the substrate, the first signal net and the second signal net, and includes an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region, such that the conductive layer overlaps with the first signal net. A fifth signal net is embedded in the substrate and between the reference plane and the outermost insulating layer.Type: GrantFiled: July 6, 2022Date of Patent: February 13, 2024Assignee: MediaTek Inc.Inventor: Nan-Jang Chen
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Patent number: 11868183Abstract: A retractable assembly includes a fixed frame, a movable frame and a plurality of first balls. The fixed frame has an accommodation portion and a plurality of guiding portions. The guiding portions are connected to the accommodation portion. The movable frame is at least partially located in the accommodation portion. The first balls are movably located in the guiding portions, and the movable frame is connected to the fixed frame via the first balls.Type: GrantFiled: February 7, 2022Date of Patent: January 9, 2024Assignee: WISTRON CORP.Inventors: Zijie Iin, Yao-Chen Yang, Chia-Jang Chen, Chih Chou Chou
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Patent number: 11855171Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.Type: GrantFiled: August 12, 2021Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Miin-Jang Chen, Sheng-Han Yi, Chen-Hsuan Lu
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Patent number: 11855066Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: May 13, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 11855190Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.Type: GrantFiled: December 13, 2022Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, COMPANY NATIONAL TAIWAN UNIVERSITYInventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
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Publication number: 20230361213Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.Type: ApplicationFiled: June 28, 2023Publication date: November 9, 2023Inventors: Miin-Jang CHEN, Po-Hsien CHENG, Yu-tung YIN
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Publication number: 20230317820Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.Type: ApplicationFiled: May 26, 2023Publication date: October 5, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
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Patent number: 11728426Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.Type: GrantFiled: July 26, 2021Date of Patent: August 15, 2023Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Miin-Jang Chen, Po-Hsien Cheng, Yu-tung Yin
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Publication number: 20230238240Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a gate dielectric layer over a semiconductor substrate; depositing a work function layer over the gate dielectric layer by an atomic layer deposition (ALD) process, wherein the work function layer comprises a metal element and a nonmetal element, and the ALD process comprises a plurality of cycles. Each of the cycles comprises: introducing a precursor gas comprising the metal element to a chamber to form a precursor surface layer on the semiconductor substrate in the chamber; purging a remaining portion of the precursor gas away from the chamber; performing a reactive-gas plasma treatment using a reactive-gas plasma comprising the nonmetal element to convert the precursor surface layer into a monolayer of the work function layer; purging a remaining portion of the reactive-gas plasma away from the chamber, and performing an inert-gas plasma treatment in the chamber.Type: ApplicationFiled: May 4, 2022Publication date: July 27, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chun-Yuan WANG, Miin-Jang CHEN
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Patent number: 11699739Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.Type: GrantFiled: January 27, 2022Date of Patent: July 11, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Tung-Ying Lee, Tse-An Chen, Tzu-Chung Wang, Miin-Jang Chen, Yu-Tung Yin, Meng-Chien Yang
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Publication number: 20230136093Abstract: A retractable assembly includes a fixed frame, a movable frame and a plurality of first balls. The fixed frame has an accommodation portion and a plurality of guiding portions. The guiding portions are connected to the accommodation portion. The movable frame is at least partially located in the accommodation portion. The first balls are movably located in the guiding portions, and the movable frame is connected to the fixed frame via the first balls.Type: ApplicationFiled: February 7, 2022Publication date: May 4, 2023Inventors: Zijie Lin, YAO-CHEN YANG, Chia-Jang Chen, Chih Chou Chou
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Publication number: 20230131796Abstract: A liquid crystal display includes a casing and a displaying module disposed in the casing. The displaying module includes a backlight module and a liquid crystal panel stacked on the backlight module. The backlight module includes a back chassis and a light-guiding plate. The back chassis has a bottom plate portion and a side portion bent from the bottom plate portion and forms an accommodating space therebetween. The back chassis has a constraining portion in the accommodating space. The light-guiding plate is accommodated in the accommodating space. At least a portion of the light-guiding plate is located between the constraining portion and the bottom plate portion.Type: ApplicationFiled: January 11, 2022Publication date: April 27, 2023Applicant: Wistron CorporationInventors: CHUNLEI ZHAO, Yao-Chen Yang, Chia-Jang Chen, Chih-Chou Chou
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Publication number: 20230112658Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu