Patents by Inventor Jang Chen

Jang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated fan-out packages
    Patent number: 10347574
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Negative Capacitance Field Effect Transistor
    Publication number: 20190207035
    Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 4, 2019
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Bo-Ting Lin
  • Methods of graphene growth and related structures
    Patent number: 10290808
    Abstract: A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 14, 2019
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Miin-Jang Chen, Samuel C. Pan, Chung-Yen Hsieh
  • VIA Structure and Methods of Forming the Same
    Publication number: 20190140173
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 9, 2019
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • HEMTs with an AlxGa1-xN barrier layer grown by plasma enhanced atomic layer deposition
    Patent number: 10269923
    Abstract: In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Wei-Hao Lee, Huan-yu Shih
  • Metallic channel device and manufacturing method thereof
    Patent number: 10269982
    Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Po-Hsien Cheng
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20190103307
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Application
    Filed: February 26, 2018
    Publication date: April 4, 2019
    Inventors: Wei-Chieh HUANG, Chin-Wei LIANG, Feng-Jia SHIU, Hsia-Wei CHEN, Jieh-Jang CHEN, Ching-Sen KUO
  • INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME
    Publication number: 20190096791
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Application
    Filed: January 22, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • HIGH-K DIELECTRIC LAYER, FABRICATING METHOD THEREOF AND MULTI-FUNCTION EQUIPMENT IMPLEMENTING SUCH FABRICATING METHOD
    Publication number: 20190088467
    Abstract: The invention discloses a high-k dielectric layer, a fabricating method thereof and a multi-function equipment implementing such fabricating method. The high-k dielectric layer of the invention includes M atomic-layer-deposited films formed in sequence on a material layer of a semiconductor device, where M is an integer larger than 1. The material layer can be a semiconductor layer, a metal layer or another dielectric layer. Each atomic-layer-deposited film is formed of an oxide and formed by an atomic layer deposition (ALD) process. N assigned films among the M atomic-layer-deposited films are bombarded by a non-reactive gas plasma during or after the cycles of the ALD process, where N is a natural number and less than or equal to M.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 21, 2019
    Inventors: Miin-Jang CHEN, Chen-Yang CHUNG
  • Semiconductor package
    Patent number: 10211134
    Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: February 19, 2019
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Semiconductor package
    Patent number: 10163767
    Abstract: A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Method For Non-Resist Nanolithography
    Publication number: 20180248020
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 30, 2018
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • Charged-Particle-Beam Patterning Without Resist
    Publication number: 20180218903
    Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 2, 2018
    Inventors: Kuen-Yu Tsai, Miin-Jang Chen, Samuel C. Pan
  • METHODS OF GRAPHENE GROWTH AND RELATED STRUCTURES
    Publication number: 20180212151
    Abstract: A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Miin-Jang CHEN, Samuel C. PAN, Chung-Yen HSIEH
  • SGS OR GSGSG PATTERN FOR SIGNAL TRANSMITTING CHANNEL, AND PCB ASSEMBLY, CHIP PACKAGE USING SUCH SGS OR GSGSG PATTERN
    Publication number: 20180206339
    Abstract: A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.
    Type: Application
    Filed: March 15, 2018
    Publication date: July 19, 2018
    Inventors: Nan-Jang Chen, Yau-Wai Wong
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180204828
    Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.
    Type: Application
    Filed: October 5, 2017
    Publication date: July 19, 2018
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Early power compensation method and apparatus thereof
    Patent number: 10019048
    Abstract: Techniques and implementations pertaining to improvements in power delivery for multi-core processors are described. A method may involve determining whether one or more processing units of a plurality of processing units are starting. The method may also involve increasing power provided to the plurality of processing units before the one or more processing units are started responsive to a determination that the one or more processing units are starting.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: July 10, 2018
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • PRINTED CIRCUIT BOARD DESIGN FOR HIGH SPEED APPLICATION
    Publication number: 20180146543
    Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 24, 2018
    Inventor: Nan-Jang Chen
  • Method for non-resist nanolithography
    Patent number: 9972702
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 15, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, National Taiwan University
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern
    Patent number: 9955581
    Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: April 24, 2018
    Assignee: MEDIATEK INC.
    Inventors: Nan-Jang Chen, Yau-Wai Wong