Patents by Inventor Jang-eun Lee
Jang-eun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250015342Abstract: An all-solid-state battery and a method of manufacturing an all solid-state battery are disclosed. The all solid-state battery includes a metal oxide and a metal capable of alloying with lithium, thus uniformly depositing lithium during charging and enabling operation at room temperature (e.g., 20-25° C.).Type: ApplicationFiled: December 6, 2023Publication date: January 9, 2025Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, Seoul National University R&DB FoundationInventors: Ji Young Kim, Kyu Joon Lee, Ga Hyeon Im, Ki Yoon Bae, Yun Sung Kim, Sam Ick Son, Jang Wook Choi, Ji Eun Lee, Ye Eun Sohn, Ji Hoon Oh, Tae Guen Lee, Noh Joon Lee
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Patent number: 12167587Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.Type: GrantFiled: April 29, 2022Date of Patent: December 10, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Eun Lee, Suk Hoon Kim, Hyo-Sub Kim
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Publication number: 20240399857Abstract: A variable-type grille apparatus may be configured for controlling the airflow rate passing through the grille and enhances marketability through advanced opening and closing operations during airflow rate control. That is, by diversifying the opening and closing operations of the grille including sequential operations, simultaneous operations, or the like, the opening and closing operations of the grille are advanced, the external designs are diversified, and the airflow rate is secured through an optimized structural arrangement. Furthermore, preventing jamming and malfunctions of components during opening and closing operations enhances the reliability of the opening and closing operations of the grille.Type: ApplicationFiled: October 26, 2023Publication date: December 5, 2024Applicants: Hyundai Motor Company, Kia Corporation, HYUNDAI MOBIS CO., LTD.Inventors: Jin Young YOON, Dong Eun CHA, Hong Heui LEE, Jae Sup BYUN, Jang Ho KIM
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Publication number: 20240400139Abstract: An active air skirt apparatus includes a base fixed to a vehicle body; a link portion including a plurality of links connected to be rotatable in a transverse direction; a drive portion mounted on the base, connected to the links of the link portion, and configured to generate rotational power to rotate the plurality of links; and a skirt provided on the base to be movable in an upward and downward direction and connected to the links of the link portion, the skirt being configured to be moved to a retracted position when the plurality of links is folded by operation of the drive portion, and moved to an extended position when the plurality of links is unfolded.Type: ApplicationFiled: November 6, 2023Publication date: December 5, 2024Applicants: Hyundai Motor Company, Kia Corporation, HYUNDAI MOBIS CO., LTD. SeoulInventors: Jin Young YOON, Chang Young LEE, Hong Heui LEE, Geon Hwi LIM, Dong Eun CHA, Myung Eun KIM, Jae Sup BYUN, Jang Ho KIM
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Publication number: 20240370115Abstract: A touch device includes a touch panel including touch electrodes, and a touch driver adjacent to the touch panel, configured to sense a touch of a user, configured to transmit uplink signals including position information of the touch electrodes to an active pen through at least some of the touch electrodes in a first touch period, and configured to receive a sensing signal including position information of the active pen, which is calculated using the uplink signals, from the active pen in a second touch period after the first touch period.Type: ApplicationFiled: November 13, 2023Publication date: November 7, 2024Inventors: Keum Dong JUNG, Jang Hui KIM, Sang Hun PARK, Yong Sub SO, Da Eun YI, Bo Hwan LEE, Byeong Kyu JEON
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Publication number: 20240306370Abstract: A semiconductor memory device includes a substrate having an element separation film defining active areas; and gate structures in trenches on the substrate and intersecting the active areas, wherein each of the gate structures includes a gate insulating layer extending along sidewalls and a bottom surface of a corresponding one of the trenches, a gate electrode layer on the gate insulating layer and including a first metal layer and a second metal layer on the first metal layer, a liner film between the gate insulating layer and the first metal layer and including a same metal material as the first and second metal layers, and a capping film in contact with the second metal layer.Type: ApplicationFiled: December 13, 2023Publication date: September 12, 2024Inventors: Sungnam LYU, Hyo Jung NOH, Byoung Hoon LEE, Jang Eun LEE, Eul Ji JEONG
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Patent number: 12014988Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.Type: GrantFiled: June 25, 2021Date of Patent: June 18, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Eun Lee, Min Joo Lee, Wan Don Kim, Hyun Bae Lee
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Patent number: 11854979Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.Type: GrantFiled: July 19, 2021Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Eun Lee, Min Joo Lee, Wan Don Kim, Hyeon Jin Shin, Hyun Bae Lee, Hyun Seok Lim
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Publication number: 20230035899Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.Type: ApplicationFiled: April 29, 2022Publication date: February 2, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jang Eun LEE, Suk Hoon KIM, Hyo-Sub KIM
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Publication number: 20220084952Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.Type: ApplicationFiled: July 19, 2021Publication date: March 17, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jang Eun LEE, Min Joo LEE, Wan Don KIM, Hyeon Jin SHIN, Hyun Bae LEE, Hyun Seok LIM
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Publication number: 20220013467Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.Type: ApplicationFiled: June 25, 2021Publication date: January 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jang Eun LEE, Min Joo LEE, Wan Don KIM, Hyun Bae LEE
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Patent number: 10177197Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a length in a first direction, a width in a second direction perpendicular to the first direction, an exchange stiffness and an aspect ratio equal to the length divided by the width. The aspect ratio is greater than one. The exchange stiffness is not less than 2×10?6 erg/cm.Type: GrantFiled: February 12, 2016Date of Patent: January 8, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dmytro Apalkov, Shuxia Wang, Jang-Eun Lee
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Patent number: 9818931Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity.Type: GrantFiled: December 28, 2015Date of Patent: November 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng
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Publication number: 20170140804Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a length in a first direction, a width in a second direction perpendicular to the first direction, an exchange stiffness and an aspect ratio equal to the length divided by the width. The aspect ratio is greater than one. The exchange stiffness is not less than 2×10?6 erg/cm.Type: ApplicationFiled: February 12, 2016Publication date: May 18, 2017Inventors: Dmytro Apalkov, Shuxia Wang, Jang-Eun Lee
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Patent number: 9559143Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.Type: GrantFiled: December 21, 2015Date of Patent: January 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng, Dustin William Erickson
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Patent number: 9472750Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.Type: GrantFiled: December 21, 2015Date of Patent: October 18, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Xueti Tang, Dustin William Erickson, Jang-Eun Lee
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Publication number: 20160197119Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.Type: ApplicationFiled: December 21, 2015Publication date: July 7, 2016Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng, Dustin William Erickson
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Publication number: 20160197265Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity.Type: ApplicationFiled: December 28, 2015Publication date: July 7, 2016Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng
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Publication number: 20160197267Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.Type: ApplicationFiled: December 21, 2015Publication date: July 7, 2016Inventors: Xueti Tang, Dustin William Erickson, Jang-Eun Lee
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Patent number: 9373781Abstract: A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.Type: GrantFiled: February 19, 2014Date of Patent: June 21, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Xueti Tang, Jang Eun Lee