Patents by Inventor Jang-eun Lee

Jang-eun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240370115
    Abstract: A touch device includes a touch panel including touch electrodes, and a touch driver adjacent to the touch panel, configured to sense a touch of a user, configured to transmit uplink signals including position information of the touch electrodes to an active pen through at least some of the touch electrodes in a first touch period, and configured to receive a sensing signal including position information of the active pen, which is calculated using the uplink signals, from the active pen in a second touch period after the first touch period.
    Type: Application
    Filed: November 13, 2023
    Publication date: November 7, 2024
    Inventors: Keum Dong JUNG, Jang Hui KIM, Sang Hun PARK, Yong Sub SO, Da Eun YI, Bo Hwan LEE, Byeong Kyu JEON
  • Publication number: 20240306370
    Abstract: A semiconductor memory device includes a substrate having an element separation film defining active areas; and gate structures in trenches on the substrate and intersecting the active areas, wherein each of the gate structures includes a gate insulating layer extending along sidewalls and a bottom surface of a corresponding one of the trenches, a gate electrode layer on the gate insulating layer and including a first metal layer and a second metal layer on the first metal layer, a liner film between the gate insulating layer and the first metal layer and including a same metal material as the first and second metal layers, and a capping film in contact with the second metal layer.
    Type: Application
    Filed: December 13, 2023
    Publication date: September 12, 2024
    Inventors: Sungnam LYU, Hyo Jung NOH, Byoung Hoon LEE, Jang Eun LEE, Eul Ji JEONG
  • Patent number: 12014988
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 18, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang Eun Lee, Min Joo Lee, Wan Don Kim, Hyun Bae Lee
  • Patent number: 11854979
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang Eun Lee, Min Joo Lee, Wan Don Kim, Hyeon Jin Shin, Hyun Bae Lee, Hyun Seok Lim
  • Publication number: 20230035899
    Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.
    Type: Application
    Filed: April 29, 2022
    Publication date: February 2, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jang Eun LEE, Suk Hoon KIM, Hyo-Sub KIM
  • Publication number: 20220084952
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.
    Type: Application
    Filed: July 19, 2021
    Publication date: March 17, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jang Eun LEE, Min Joo LEE, Wan Don KIM, Hyeon Jin SHIN, Hyun Bae LEE, Hyun Seok LIM
  • Publication number: 20220013467
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.
    Type: Application
    Filed: June 25, 2021
    Publication date: January 13, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jang Eun LEE, Min Joo LEE, Wan Don KIM, Hyun Bae LEE
  • Patent number: 10177197
    Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a length in a first direction, a width in a second direction perpendicular to the first direction, an exchange stiffness and an aspect ratio equal to the length divided by the width. The aspect ratio is greater than one. The exchange stiffness is not less than 2×10?6 erg/cm.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dmytro Apalkov, Shuxia Wang, Jang-Eun Lee
  • Patent number: 9818931
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng
  • Publication number: 20170140804
    Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a length in a first direction, a width in a second direction perpendicular to the first direction, an exchange stiffness and an aspect ratio equal to the length divided by the width. The aspect ratio is greater than one. The exchange stiffness is not less than 2×10?6 erg/cm.
    Type: Application
    Filed: February 12, 2016
    Publication date: May 18, 2017
    Inventors: Dmytro Apalkov, Shuxia Wang, Jang-Eun Lee
  • Patent number: 9559143
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng, Dustin William Erickson
  • Patent number: 9472750
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xueti Tang, Dustin William Erickson, Jang-Eun Lee
  • Publication number: 20160197119
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Application
    Filed: December 21, 2015
    Publication date: July 7, 2016
    Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng, Dustin William Erickson
  • Publication number: 20160197265
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity.
    Type: Application
    Filed: December 28, 2015
    Publication date: July 7, 2016
    Inventors: Xueti Tang, Jang-Eun Lee, Gen Feng
  • Publication number: 20160197267
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.
    Type: Application
    Filed: December 21, 2015
    Publication date: July 7, 2016
    Inventors: Xueti Tang, Dustin William Erickson, Jang-Eun Lee
  • Patent number: 9373781
    Abstract: A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: June 21, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xueti Tang, Jang Eun Lee
  • Patent number: 9356228
    Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Heon Park, Woo Chang Lim, Se Chung Oh, Young Hyun Kim, Sang Hwan Park, Jang Eun Lee
  • Patent number: 9306155
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer includes at least one of a hybrid perpendicular magnetic anisotropy (PMA) structure and tetragonal bulk perpendicular magnetic anisotropy (B-PMA) structure. At least one of the free layer and the pinned layer have a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xueti Tang, Jang Eun Lee
  • Patent number: 9159914
    Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyung Yim, In-Gyu Baek, Jang-Eun Lee, Se-Chung Oh, Kyung-Tae Nam, Jin-Shi Zhao
  • Patent number: 9065039
    Abstract: Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 23, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Heon Park, Woo Chang Lim, Se Chung Oh, Woo Jin Kim, Sang Hwan Park, Jang Eun Lee