Abstract: A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive layer and the tunneling layer may support transition between first and second resistance states responsive to first and second voltages applied across the first and second electrodes. The first and second voltages may have opposite polarities.

Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract: A nonvolatile memory device includes a first electrode and a second electrode, and a variable resistor interposed between the first and second electrodes. The variable resistor has a critical voltage, and a resistance-voltage characteristic of the variable resistor is switched at a voltage higher than the critical voltage, so that a resistance of the variable resistor is higher at a read voltage applied after the switching of the resistance-voltage curve than at a read voltage applied before the switching of the resistance-voltage curve. Methods of operating a nonvolatile memory device include setting a plurality of write voltages higher than an initial critical voltage, assigning respective data values to states in which a resistance-voltage characteristic is switched at the write voltages, setting a read voltage lower than the initial critical voltage, and reading the data values by measuring current flowing through the variable resistor in response to the read voltage.

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract: A magnetic random access memory (MRAM), and a method of manufacturing the same, includes a switching device and a magnetic tunneling junction (MTJ) cell connected to the switching device, wherein the MTJ cell includes a pinned film having a metal film and a magnetic film, the magnetic film enclosing the metal film.

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract: Methods of programming a RRAM device are provided. An increasing set current is applied to a data storing layer pattern of the RRAM device while measuring a resistance of the data storing layer pattern until the resistance indicates a set state in the data storing layer pattern. An increasing reset voltage is applied to the data storing layer pattern of the RRAM device while measuring the resistance of the data storing layer pattern until the resistance indicates a reset state in the data storing layer pattern.

Abstract: A magnetic random access memory (MRAM), and a method of manufacturing the same, includes a switching device and a magnetic tunneling junction (MTJ) cell connected to the switching device, wherein the MTJ cell includes a pinned film having a metal film and a magnetic film, the magnetic film enclosing the metal film.

Abstract: A method for forming a minute pattern includes depositing a material layer on a semiconductor substrate having a conductive region, forming a first mask layer on the material layer, forming a recess region in the first mask layer, performing layer processing to form a first mask pattern in the recess region, and etching the material layer to form a material layer pattern.

Abstract: A magnetic memory device includes a pinning layer, a pinned layer, an insulation layer, which are sequentially stacked on a semiconductor substrate. The magnetic memory device further includes a free layer disposed on the insulation layer, a capping layer disposed on the free layer and an MR (magnetoresistance) enhancing layer interposed between the free layer and the capping layer. The MR enhancing layer is formed of at least one anti-ferromagnetic material.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract: A Resistance based Random Access Memory (ReRAM) can include a current reference circuit including at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits.

Abstract: A method of writing to magnetic random access memory (MRAM) devices is provided. The method includes preparing a digit line disposed on a semiconductor substrate, a bit line crossing over the digit line, and a magnetic tunnel junction (MTJ) interposed between the digit line and the bit line. The MTJ has a pinned layer, a tunneling insulating layer, and a synthetic anti-ferromagnetic (SAF) free layer which are sequentially stacked. In addition, the SAF free layer has a bottom free layer and a top free layer which are separated by an exchange spacer layer. An initial magnetization state of the MTJ is read and compared with a desired magnetization state. When the initial magnetization state is different from the desired magnetization state, a first write line pulse is applied to one of the digit line and the bit line, and a second write line pulse is applied to the other of the digit line and the bit line, thereby changing the magnetization state of the MTJ.

Abstract: A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.

Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.