Abstract: Provided is a method and apparatus for compressing a text and an image. When compressing the text and image, it is possible to group valid lines with data into each line having a common element, and compress and encode the data of the valid lines. Accordingly, it is possible to reduce a data loss that may occur in a tactical communication environment with a poor channel state due to a bit sleep or a burst error. In the case of the text, it is possible to perform lossless compression on only a valid line with data and thereby improve compression efficiency. In the case of the image, it is possible to perform loss compression on valid lines, and then restore the partially damaged data using an ECC even when data is partially damaged. Accordingly, it is possible to improve compression efficiency and the entire data transmission success rate.

Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Abstract: There are provided a digital RF converter capable of improving a dynamic range and a signal to noise ratio of a transmitter and a digital RF modulator and a transmitter including the same. The digital RF converter may include: a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed; a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed; and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

Abstract: Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.

Abstract: Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes.

Abstract: There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing the signal of an input port of the digitally controlled oscillator to pass through a frequency table and a frequency-to-digital code mapper in sequence and correcting an input of the digitally controlled oscillator by performing negative feedback to an input port of the first filter; and a frequency table generator storing a frequency value of an output signal of the digitally controlled oscillator in the frequency table.

Abstract: A parallel processing shrinking key generator is provided. The parallel processing shrinking key generator includes: a selection linear feedback shift register (LFSR); a source LFSR; a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal; and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter.

Abstract: There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing the signal of an input port of the digitally controlled oscillator to pass through a frequency table and a frequency-to-digital code mapper in sequence and correcting an input of the digitally controlled oscillator by performing negative feedback to an input port of the first filter; and a frequency table generator storing a frequency value of an output signal of the digitally controlled oscillator in the frequency table.

Abstract: Provided is a method and apparatus for compressing a text and an image. When compressing the text and image, it is possible to group valid lines with data into each line having a common element, and compress and encode the data of the valid lines. Accordingly, it is possible to reduce a data loss that may occur in a tactical communication environment with a poor channel state due to a bit sleep or a burst error. In the case of the text, it is possible to perform lossless compression on only a valid line with data and thereby improve compression efficiency. In the case of the image, it is possible to perform loss compression on valid lines, and then restore the partially damaged data using an ECC even when data is partially damaged. Accordingly, it is possible to improve compression efficiency and the entire data transmission success rate.

Abstract: The present invention provides an organic/inorganic composite porous separator, which comprises: (a) a porous substrate having pores; and (b) an organic/inorganic composite layer formed by coating at least one region selected from the group consisting of a surface of the substrate and a part of pores present in the substrate with a mixture of inorganic porous particles and a binder polymer, wherein the inorganic porous particles have a plurality of macropores with a diameter of 50nm or greater in the particle itself thereby form a pore structure, a manufacturing method thereof, and an electrochemical device using the same. As an additional pathway for lithium ions is created due to a number of pores existing in the inorganic porous particle itself, degradation in the battery performance can be minimized, and energy density per unit weight can be increased by the weight loss effect.

Abstract: Disclosed is an electrolyte for a battery comprising: (a) an electrolyte salt; (b) an organic solvent; and (c) a functional electrolyte additive. An electrochemical device comprising the electrolyte is also disclosed. The additive used in the electrochemical device effectively controls the surface of a cathode active material, which otherwise causes side reactions with an electrolyte, due to the basic skeleton structure and polar side branches of the additive. Therefore, it is possible to improve the safety of a battery, while not adversely affecting the quality of a battery.

Abstract: Disclosed is an electrode, comprising a coating layer of crosslinked polymer, formed on a surface of electrode active material particles, while maintaining a pore structure formed among the electrode active material particles interconnected to each other in the electrode. A method for manufacturing the electrode and an electrochemical device comprising the electrode are also disclosed. The electrode, which comprises a coating layer of crosslinked polymer formed on the surface of the electrode active material particles, can improve the safety of a battery, while minimizing degradation in the quality of a battery.

Abstract: A parallel processing shrinking key generator is provided. The parallel processing shrinking key generator includes: a selection linear feedback shift register (LFSR); a source LFSR; a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal, and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter.

Abstract: The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

Abstract: The present invention relates to a structure of a delta-sigma factional divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma factional divider the structure is simple and that can obtain an effect of a delta sigma mode while having a wide-band frequency mixing capability.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a main surface. A bonding pad is formed on the main surface. A multi-layer wiring structure is disposed between the main surface and the bonding pad. The multi-layer wiring structure includes a first wiring layer, a second wiring layer, and an interlayer insulating film therebetween. The first layer, the second layer, and the interlayer film form a capacitor disposed under the bonding pad.

Abstract: A seat structure for a ball valve which includes a seat member formed by rolling up an alternate stack of a thin steel plate and a thin graphite plate. The seat member is provided with a fixture portion fixed into an inner periphery of the valve body and a ball contact which is in contact with a surface of a valve ball provided between the inflow vent side and the outflow vent side. The seat structure improves an anti-abrasion and enables a secure functioning of the ball valve at a high temperature and high pressure.

Abstract: The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.