Abstract: The present disclosure provides an electrical device including a battery cell, a voltage sensor operatively coupled to the battery cell in order to measure a voltage level of the battery cell, a current sensor operatively coupled to the battery cell in order to measure an amount of current drawn from or supplied to the battery cell, and a battery management system (BMS). The battery management system includes a controller In communication with the voltage sensor and the current sensor. The controller is configured to execute a program stored in the BMS to calculate a state of health of the individual battery electrodes comprising a battery cell using a first differential voltage point, a second differential voltage point, and a characteristic curve of a fresh battery electrode of a fresh battery cell, wherein the battery cell includes a second battery electrode not exhibiting distinct phase transitions during a charge-discharge cycle.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

Abstract: A device for managing applications installed on the device and a method thereof are provided. The device includes a controller configured to obtain driving information of the applications in response to the applications being executed, and determine an application satisfying an uninstall condition, among the applications, based on the driving information. The device further includes an interface configured to change a display of an object indicating the determined application, based on the uninstall condition.

Abstract: A method of estimating a state of health of a battery, the method being performed by a computing apparatus, the method including: preparing a trained artificial neural network; generating input data by measuring at least one parameter of a battery; acquiring a plurality of output values each corresponding to a plurality of classes by inputting the input data into the trained artificial neural network; and generating a state of health estimation value of the battery using a plurality of preset health state sections each corresponding to the plurality of classes and the plurality of output values each corresponding to the plurality of classes.

Abstract: Disclosed are a polyolefin resin composition and a production method using same. The polyolefin resin satisfies the following conditions: (1) melt index (MI2.16, 190° C., under a load of 2.16 kg) is 0.1 to 1.5 g/10 min; (2) density is 0.91 to 0.93 g/cc; (3) polydispersity Index (Mw (weight-average molecular weight)/Mn (number-average molecular weight)) is 3 to 7; (4) Mz (Z-average molecular weight)/Mw (weight-average molecular weight) is 2.3 to 4.5; and (5) COI (Comonomer Orthogonal Index) value calculated by Equation 1 in the specification is 5 to 12. In Equation 1, “SCB number at Mz” represents average number of branches derived from comonomers per 1000 carbon atoms at Z-average molecular weight (Mz), and “SCB number at Mn” represents average number of branches derived from comonomers per 1000 carbon atoms at number-average molecular weight (Mn) based on a molecular weight-comonomer distribution graph.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: A terminal device is disclosed. The terminal device includes, for example: a communication interface configured to receive UI information set in another terminal device; input circuitry configured to receive selection of UI setting to be applied to the terminal device from among UIs set in another terminal device based on the received UI information; a controller configured to set a UI of the terminal device based on the selected UI setting; and a display configured to display the set UI.

Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

Abstract: A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.

Abstract: A terminal device is disclosed. The terminal device includes, for example: a communication interface configured to receive UI information set in another terminal device; input circuitry configured to receive selection of UI setting to be applied to the terminal device from among UIs set in another terminal device based on the received UI information; a controller configured to set a UI of the terminal device based on the selected UI setting; and a display configured to display the set UI.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: A catalyst composition for polymerizing a polyolefin having excellent processability and impact strength, a process for producing a polyolefin and a polyolefin resin thereof are disclosed. The catalyst composition comprises at least one first organometallic compound of following formula 1; at least one second organometallic compound of following formula 2; and aluminoxane. The polyolefin resin satisfies following properties (i) to (iv) and (vi), (i) melt flow index (ASTM D1238), measured at 190° C., under a load of 2.16 kg: 0.1 to 1.5 g/10 min, (ii) density: 910 to 930 kg/m3, (iii) the ratio (Mw/Mn), as measured by gel permeation chromatography (GPC):3.0 to 7.0, (iv) the ratio (Mz/Mw), as measured by GPC: 2.2 to 4.5, and (vi) when the TREF curve of multimodal distribution is deconvoluted, the area of TREF curve having a peak at 50 to 74° C. is 40 to 75% of the total area of the TREF curve.

Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: A device for managing applications installed on the device and a method thereof are provided. The device includes a controller configured to obtain driving information of the applications in response to the applications being executed, and determine an application satisfying an uninstall condition, among the applications, based on the driving information. The device further includes an interface configured to change a display of an object indicating the determined application, based on the uninstall condition.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.